diff options
Diffstat (limited to 'dts/upstream/Bindings/spmi')
3 files changed, 144 insertions, 10 deletions
diff --git a/dts/upstream/Bindings/spmi/hisilicon,hisi-spmi-controller.yaml b/dts/upstream/Bindings/spmi/hisilicon,hisi-spmi-controller.yaml index f882903769f..3ccf35de371 100644 --- a/dts/upstream/Bindings/spmi/hisilicon,hisi-spmi-controller.yaml +++ b/dts/upstream/Bindings/spmi/hisilicon,hisi-spmi-controller.yaml @@ -14,7 +14,7 @@ description: | It is a MIPI System Power Management (SPMI) controller. The PMIC part is provided by - ./Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml. + Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml. allOf: - $ref: spmi.yaml# @@ -48,26 +48,23 @@ patternProperties: PMIC properties, which are specific to the used SPMI PMIC device(s). When used in combination with HiSilicon 6421v600, the properties are documented at - drivers/staging/hikey9xx/hisilicon,hi6421-spmi-pmic.yaml. + Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml unevaluatedProperties: false examples: - | - bus { - #address-cells = <2>; - #size-cells = <2>; + #include <dt-bindings/spmi/spmi.h> - spmi: spmi@fff24000 { + spmi@fff24000 { compatible = "hisilicon,kirin970-spmi-controller"; + reg = <0xfff24000 0x1000>; #address-cells = <2>; #size-cells = <0>; - reg = <0x0 0xfff24000 0x0 0x1000>; hisilicon,spmi-channel = <2>; pmic@0 { - reg = <0 0>; - /* pmic properties */ + reg = <0 SPMI_USID>; + /* pmic properties */ }; - }; }; diff --git a/dts/upstream/Bindings/spmi/qcom,spmi-pmic-arb.yaml b/dts/upstream/Bindings/spmi/qcom,spmi-pmic-arb.yaml index f983b4af6db..51daf1b847a 100644 --- a/dts/upstream/Bindings/spmi/qcom,spmi-pmic-arb.yaml +++ b/dts/upstream/Bindings/spmi/qcom,spmi-pmic-arb.yaml @@ -92,6 +92,7 @@ properties: description: > SPMI bus instance. only applicable to PMIC arbiter version 7 and beyond. Supported values, 0 = primary bus, 1 = secondary bus + deprecated: true required: - compatible diff --git a/dts/upstream/Bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml b/dts/upstream/Bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml new file mode 100644 index 00000000000..a28b70fb330 --- /dev/null +++ b/dts/upstream/Bindings/spmi/qcom,x1e80100-spmi-pmic-arb.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm X1E80100 SPMI Controller (PMIC Arbiter v7) + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + +description: | + The X1E80100 SPMI PMIC Arbiter implements HW version 7 and it's an SPMI + controller with wrapping arbitration logic to allow for multiple on-chip + devices to control up to 2 SPMI separate buses. + + The PMIC Arbiter can also act as an interrupt controller, providing interrupts + to slave devices. + +properties: + compatible: + const: qcom,x1e80100-spmi-pmic-arb + + reg: + items: + - description: core registers + - description: tx-channel per virtual slave registers + - description: rx-channel (called observer) per virtual slave registers + + reg-names: + items: + - const: core + - const: chnls + - const: obsrvr + + ranges: true + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + + qcom,ee: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 5 + description: > + indicates the active Execution Environment identifier + + qcom,channel: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 5 + description: > + which of the PMIC Arb provided channels to use for accesses + +patternProperties: + "^spmi@[a-f0-9]+$": + type: object + $ref: /schemas/spmi/spmi.yaml + unevaluatedProperties: false + + properties: + reg: + items: + - description: configuration registers + - description: interrupt controller registers + + reg-names: + items: + - const: cnfg + - const: intr + + interrupts: + maxItems: 1 + + interrupt-names: + const: periph_irq + + interrupt-controller: true + + '#interrupt-cells': + const: 4 + description: | + cell 1: slave ID for the requested interrupt (0-15) + cell 2: peripheral ID for requested interrupt (0-255) + cell 3: the requested peripheral interrupt (0-7) + cell 4: interrupt flags indicating level-sense information, + as defined in dt-bindings/interrupt-controller/irq.h + +required: + - compatible + - reg-names + - qcom,ee + - qcom,channel + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + spmi: arbiter@c400000 { + compatible = "qcom,x1e80100-spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x4000000>, + <0 0x0c440000 0 0x80000>; + reg-names = "core", "chnls", "obsrvr"; + + qcom,ee = <0>; + qcom,channel = <0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + spmi_bus0: spmi@c42d000 { + reg = <0 0x0c42d000 0 0x4000>, + <0 0x0c4c0000 0 0x10000>; + reg-names = "cnfg", "intr"; + + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + }; + }; |