aboutsummaryrefslogtreecommitdiff
path: root/dts/upstream/src/arm64/freescale/fsl-ls1012a-frwy.dts
diff options
context:
space:
mode:
Diffstat (limited to 'dts/upstream/src/arm64/freescale/fsl-ls1012a-frwy.dts')
-rw-r--r--dts/upstream/src/arm64/freescale/fsl-ls1012a-frwy.dts44
1 files changed, 44 insertions, 0 deletions
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1012a-frwy.dts b/dts/upstream/src/arm64/freescale/fsl-ls1012a-frwy.dts
new file mode 100644
index 00000000000..e8562585d4a
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1012a-frwy.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for Freescale LS1012A FRWY Board.
+ *
+ * Copyright 2018 NXP
+ *
+ * Pramod Kumar <pramod.kumar_1@nxp.com>
+ *
+ */
+/dts-v1/;
+
+#include "fsl-ls1012a.dtsi"
+
+/ {
+ model = "LS1012A FRWY Board";
+ compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+
+ w25q16dw0: flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+};