diff options
Diffstat (limited to 'dts/upstream/src/arm64/microchip/sparx5_pcb135_emmc.dts')
| -rw-r--r-- | dts/upstream/src/arm64/microchip/sparx5_pcb135_emmc.dts | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/dts/upstream/src/arm64/microchip/sparx5_pcb135_emmc.dts b/dts/upstream/src/arm64/microchip/sparx5_pcb135_emmc.dts new file mode 100644 index 00000000000..f82266fe2ad --- /dev/null +++ b/dts/upstream/src/arm64/microchip/sparx5_pcb135_emmc.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; +#include "sparx5_pcb135_board.dtsi" + +/ { + model = "Sparx5 PCB135 Reference Board (eMMC enabled)"; + compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x10000000>; + }; +}; + +&gpio { + emmc_pins: emmc-pins { + /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" + * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) + */ + pins = "GPIO_34", "GPIO_38", "GPIO_39", + "GPIO_40", "GPIO_41", "GPIO_42", + "GPIO_43", "GPIO_44", "GPIO_45", + "GPIO_46", "GPIO_47"; + drive-strength = <3>; + function = "emmc"; + }; +}; + +&sdhci0 { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + non-removable; + max-frequency = <52000000>; + bus-width = <8>; + microchip,clock-delay = <10>; +}; |