diff options
Diffstat (limited to 'dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi')
| -rw-r--r-- | dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi | 447 |
1 files changed, 447 insertions, 0 deletions
diff --git a/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi b/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi new file mode 100644 index 00000000000..8feab931764 --- /dev/null +++ b/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for AM6 SoC Family MCU Domain peripherals + * + * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_conf: scm-conf@40f00000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x40f00000 0x0 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40f00000 0x20000>; + + phy_gmii_sel: phy@4040 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4040 0x4>; + #phy-cells = <1>; + }; + }; + + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04200 0x0 0x10>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000101>; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04280 0x0 0x8>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000003>; + }; + + mcu_uart0: serial@40a00000 { + compatible = "ti,am654-uart"; + reg = <0x00 0x40a00000 0x00 0x100>; + interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <96000000>; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcu_ram: sram@41c00000 { + compatible = "mmio-sram"; + reg = <0x00 0x41c00000 0x00 0x80000>; + ranges = <0x0 0x00 0x41c00000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + mcu_i2c0: i2c@40b00000 { + compatible = "ti,am654-i2c", "ti,omap4-i2c"; + reg = <0x0 0x40b00000 0x0 0x100>; + interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "fck"; + clocks = <&k3_clks 114 1>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x40300000 0x0 0x400>; + interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 142 1>; + power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x40310000 0x0 0x400>; + interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 143 1>; + power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x40320000 0x0 0x400>; + interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 144 1>; + power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; + reg = <0x0 0x40200000 0x0 0x1000>; + interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 0 2>; + assigned-clocks = <&k3_clks 0 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&mcu_udmap 0x7100>, + <&mcu_udmap 0x7101 >; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am654-adc", "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; + reg = <0x0 0x40210000 0x0 0x1000>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 1 2>; + assigned-clocks = <&k3_clks 1 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&mcu_udmap 0x7102>, + <&mcu_udmap 0x7103>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am654-adc", "ti,am3359-adc"; + }; + }; + + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + clocks = <&k3_clks 35 0>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + clocks = <&k3_clks 36 0>; + clock-names = "fck"; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + clocks = <&k3_clks 37 0>; + clock-names = "fck"; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + clocks = <&k3_clks 38 0>; + clock-names = "fck"; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_navss: bus@28380000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; + dma-coherent; + dma-ranges; + + ti,sci-dev-id = <119>; + + mcu_ringacc: ringacc@2b800000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", + "proxy_target", "cfg"; + ti,num-rings = <286>; + ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ + ti,sci = <&dmsc>; + ti,sci-dev-id = <195>; + msi-parent = <&inta_main_udmass>; + }; + + mcu_udmap: dma-controller@285c0000 { + compatible = "ti,am654-navss-mcu-udmap"; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchanrt", "tchanrt", + "tchan", "rchan", "rflow"; + msi-parent = <&inta_main_udmass>; + #dma-cells = <1>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <194>; + ti,ringacc = <&mcu_ringacc>; + + ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ + <0xd>; /* TX_CHAN */ + ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ + <0xa>; /* RX_CHAN */ + ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ + }; + }; + + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x2a480000 0x0 0x80000>, + <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + + m_can0: can@40528000 { + compatible = "bosch,m_can"; + reg = <0x0 0x40528000 0x0 0x400>, + <0x0 0x40500000 0x0 0x4400>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 5>, <&k3_clks 102 0>; + clock-names = "hclk", "cclk"; + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + m_can1: can@40568000 { + compatible = "bosch,m_can"; + reg = <0x0 0x40568000 0x0 0x400>, + <0x0 0x40540000 0x0 0x4400>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 5>, <&k3_clks 103 0>; + clock-names = "hclk", "cclk"; + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + fss: bus@47000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ + <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ + <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ + <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* OSPI0 Memory */ + <0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */ + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x0 0x47040000 0x0 0x100>, + <0x5 0x00000000 0x1 0x0000000>; + interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 248 0>; + assigned-clocks = <&k3_clks 248 0>; + assigned-clock-parents = <&k3_clks 248 2>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x0 0x47050000 0x0 0x100>, + <0x7 0x00000000 0x1 0x00000000>; + interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 249 6>; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + mcu_cpsw: ethernet@46000000 { + compatible = "ti,am654-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x46000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; + dma-coherent; + clocks = <&k3_clks 5 10>; + clock-names = "fck"; + power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&mcu_udmap 0xf000>, + <&mcu_udmap 0xf001>, + <&mcu_udmap 0xf002>, + <&mcu_udmap 0xf003>, + <&mcu_udmap 0xf004>, + <&mcu_udmap 0xf005>, + <&mcu_udmap 0xf006>, + <&mcu_udmap 0xf007>, + <&mcu_udmap 0x7000>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + ti,syscon-efuse = <&mcu_conf 0x200>; + phys = <&phy_gmii_sel 1>; + }; + }; + + davinci_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 5 10>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&mcu_cpsw_cpts_mux>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + + mcu_cpsw_cpts_mux: refclk-mux { + #clock-cells = <0>; + clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, + <&k3_clks 118 6>, <&k3_clks 118 3>, + <&k3_clks 118 8>, <&k3_clks 118 14>, + <&k3_clks 120 3>, <&k3_clks 121 3>; + assigned-clocks = <&mcu_cpsw_cpts_mux>; + assigned-clock-parents = <&k3_clks 118 5>; + }; + }; + }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,am654-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,am654-r5f"; + reg = <0x41000000 0x00008000>, + <0x41010000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <159>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 159 1>; + firmware-name = "am65x-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,am654-r5f"; + reg = <0x41400000 0x00008000>, + <0x41410000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <245>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 245 1>; + firmware-name = "am65x-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + mcu_rti1: watchdog@40610000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x0 0x40610000 0x0 0x100>; + clocks = <&k3_clks 135 0>; + power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>; + assigned-clocks = <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 135 4>; + }; +}; |