diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/mccmon6.h | 321 | ||||
| -rw-r--r-- | include/configs/mx6qsabreauto.h | 1 | ||||
| -rw-r--r-- | include/configs/mx6sxsabreauto.h | 7 | ||||
| -rw-r--r-- | include/configs/nitrogen6x.h | 2 | ||||
| -rw-r--r-- | include/configs/udoo_neo.h | 4 | ||||
| -rw-r--r-- | include/dt-bindings/clock/imx6sx-clock.h | 280 |
6 files changed, 606 insertions, 9 deletions
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h new file mode 100644 index 00000000000..e7223fb714a --- /dev/null +++ b/include/configs/mccmon6.h @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2016-2017 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config_distro_defaults.h> +#include "mx6_common.h" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#include "imx6_spl.h" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) +#define CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000) +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000) +#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K) +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 + +/* + * Below defines are set but NOT really used since we by + * design force U-Boot run when we boot in development + * mode from SD card (SD2) + */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800) +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000) +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) + +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#undef CONFIG_SYS_NO_FLASH +/* NOR 16-bit mode */ +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_FLASH_VERIFY + +/* NOR Flash MTD */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } +#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } + +/* MTD support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +#define MTDIDS_DEFAULT "nor0=8000000.nor" +#define MTDPARTS_DEFAULT \ + "mtdparts=8000000.nor:" \ + "32m@0x0(mccmon6-image.nor)," \ + "256k@0x40000(u-boot-env.nor)," \ + "1m@0x80000(u-boot.nor)," \ + "8m@0x180000(kernel.nor)," \ + "8m@0x980000(swupdate-kernel.nor)," \ + "8m@0x1180000(swupdate-rootfs.nor)," \ + "128k@0x1980000(kernel-dtb.nor)," \ + "128k@0x19C0000(swupdate-kernel-dtb.nor)" + +/* USB Configs */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* Ethernet Configuration */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 1 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdtfile=imx6q-mccmon6.dtb\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "boot_os=yes\0" \ + "download_kernel=" \ + "tftpboot ${kernel_addr} ${kernel_file};" \ + "tftpboot ${fdt_addr} ${fdtfile};\0" \ + "get_boot_medium=" \ + "setenv boot_medium nor;" \ + "setexpr.l _src_sbmr1 *0x020d8004;" \ + "setexpr _b_medium ${_src_sbmr1} '&' 0x00000040;" \ + "if test ${_b_medium} = 40; then " \ + "setenv boot_medium sdcard;" \ + "fi\0" \ + "kernel_file=uImage\0" \ + "load_kernel=" \ + "load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \ + "load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \ + "boot_sd=" \ + "echo '#######################';" \ + "echo '# Factory SDcard Boot #';" \ + "echo '#######################';" \ + "setenv mmcdev 1;" \ + "setenv mmcfactorydev 0;" \ + "setenv mmcfactorypart 1;" \ + "run factory_flash_img;\0" \ + "boot_nor=" \ + "setenv kernelnor 0x08180000;" \ + "setenv dtbnor 0x09980000;" \ + "setenv bootargs console=${console} quiet " \ + ""MTDPARTS_DEFAULT" " \ + "root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \ + "cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \ + "bootm ${kernelnor} - ${dtbloadaddr};\0" \ + "boot_recovery=" \ + "echo '#######################';" \ + "echo '# RECOVERY SWU Boot #';" \ + "echo '#######################';" \ + "setenv rootfsloadaddr 0x13000000;" \ + "setenv swukernelnor 0x08980000;" \ + "setenv swurootfsnor 0x09180000;" \ + "setenv swudtbnor 0x099A0000;" \ + "setenv bootargs console=${console} " \ + ""MTDPARTS_DEFAULT" " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}::off root=/dev/ram rw;" \ + "cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \ + "cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \ + "bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \ + "boot_tftp=" \ + "echo '#######################';" \ + "echo '# TFTP Boot #';" \ + "echo '#######################';" \ + "if run download_kernel; then " \ + "setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rootwait;" \ + "bootm ${kernel_addr} - ${fdt_addr};" \ + "fi\0" \ + "bootcmd=" \ + "if test -n ${recovery_status}; then " \ + "run boot_recovery;" \ + "else " \ + "if test ! -n ${boot_medium}; then " \ + "run get_boot_medium;" \ + "if test ${boot_medium} = sdcard; then " \ + "run boot_sd;" \ + "else " \ + "run boot_nor;" \ + "fi;" \ + "else " \ + "if test ${boot_medium} = tftp; then " \ + "run boot_tftp;" \ + "fi;" \ + "fi;" \ + "fi\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "fdt_addr=0x18000000\0" \ + "bootdev=1\0" \ + "bootpart=1\0" \ + "kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \ + "netdev=eth0\0" \ + "load_addr=0x11000000\0" \ + "dtbloadaddr=0x12000000\0" \ + "uboot_file=u-boot.img\0" \ + "SPL_file=SPL\0" \ + "load_uboot=tftp ${load_addr} ${uboot_file}\0" \ + "nor_img_addr=0x11000000\0" \ + "nor_img_file=core-image-lwn-mccmon6.nor\0" \ + "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \ + "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ + "nor_img_size=0x02000000\0" \ + "factory_script_file=factory.scr\0" \ + "factory_load_script=" \ + "if test -e mmc ${mmcdev}:${mmcfactorypart} " \ + "${factory_script_file}; then " \ + "load mmc ${mmcdev}:${mmcfactorypart} " \ + "${loadaddr} ${factory_script_file};" \ + "fi\0" \ + "factory_script=echo Running factory script from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "factory_flash_img="\ + "echo 'Flash mccmon6 with factory images'; " \ + "if run factory_load_script; then " \ + "run factory_script;" \ + "else " \ + "echo No factory script: ${factory_script_file} found on " \ + "device ${mmcdev};" \ + "run factory_nor_img;" \ + "run factory_eMMC_img;" \ + "fi\0" \ + "factory_eMMC_img="\ + "echo 'Update mccmon6 eMMC image'; " \ + "if load mmc ${mmcdev}:${mmcfactorypart} " \ + "${loadaddr} ${emmc_img_file}; then " \ + "setexpr fw_sz ${filesize} / 0x200;" \ + "setexpr fw_sz ${fw_sz} + 1;" \ + "mmc dev ${mmcfactorydev};" \ + "mmc write ${loadaddr} 0x0 ${fw_sz};" \ + "fi\0" \ + "factory_nor_img="\ + "echo 'Update mccmon6 NOR image'; " \ + "if load mmc ${mmcdev}:${mmcfactorypart} " \ + "${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "nor_update=" \ + "protect off ${nor_bank_start} +${nor_img_size};" \ + "erase ${nor_bank_start} +${nor_img_size};" \ + "setexpr nor_img_size ${nor_img_size} / 4; " \ + "cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \ + "tftp_nor_uboot="\ + "echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \ + "setenv nor_img_file u-boot.img; " \ + "setenv nor_img_size 0x80000; " \ + "setenv nor_bank_start 0x08080000; " \ + "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "tftp_nor_uImg="\ + "echo 'Update mccmon6 NOR uImage via TFTP'; " \ + "setenv nor_img_file uImage; " \ + "setenv nor_img_size 0x500000; " \ + "setenv nor_bank_start 0x08180000; " \ + "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "tftp_nor_img="\ + "echo 'Update mccmon6 NOR image via TFTP'; " \ + "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ + "run nor_update;" \ + "fi\0" \ + "tftp_nor_SPL="\ + "if tftp ${load_addr} SPL_padded; then " \ + "erase 0x08000000 +0x20000;" \ + "cp.b ${load_addr} 0x08000000 0x20000;" \ + "fi;\0" \ + "tftp_sd_SPL="\ + "if mmc dev 1; then " \ + "if tftp ${load_addr} ${SPL_file}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${load_addr} 0x2 ${fw_sz};" \ + "fi;" \ + "fi;\0" \ + "tftp_sd_uboot="\ + "if mmc dev 1; then " \ + "if run load_uboot; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${load_addr} 0x8A ${fw_sz};" \ + "fi;" \ + "fi;\0" + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_SIZE (SZ_128K) + +/* Envs are stored in NOR flash */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (SZ_128K) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x60000) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#endif /* __CONFIG_H * */ diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index f849f3420a5..7d68633c78d 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -38,6 +38,7 @@ #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ #define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_FSL_USDHC_NUM 2 #if defined(CONFIG_ENV_IS_IN_MMC) diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 90a935bbd07..0742b4bf2ec 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -114,19 +114,12 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR /* I2C Configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - /* NAND flash command */ #define CONFIG_CMD_NAND #define CONFIG_CMD_NAND_TRIMFFS diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index ca55063f77c..efa5065d9ba 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -136,6 +136,7 @@ "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ + "usb_pgood_delay=2000\0" \ "mmcdevs=0 1\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ @@ -205,6 +206,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootdevs=" CONFIG_DRIVE_TYPES "\0" \ "umsdevs=" CONFIG_UMSDEVS "\0" \ + "usb_pgood_delay=2000\0" \ "console=ttymxc1\0" \ "clearenv=if sf probe || sf probe || sf probe 1 ; then " \ "sf erase 0xc0000 0x2000 && " \ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 9835ce88753..23a3685bcd5 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -34,6 +34,7 @@ "initrd_high=0xffffffff\0" \ "fdtfile=undefined\0" \ "fdt_addr=0x83000000\0" \ + "fdt_addr_r=0x83000000\0" \ "ip_dyn=yes\0" \ "mmcdev=0\0" \ "mmcrootfstype=ext4\0" \ @@ -47,11 +48,10 @@ "if test $board_name = EXTENDED; then " \ "setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \ "if test $fdtfile = UNDEFINED; then " \ - "echo WARNING: Could not determine dtb to use; fi; \0" \ + "echo WARNING: Could not determine dtb to use; fi\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "ramdisk_addr_r=0x83000000\0" \ - "ramdiskaddr=0x83000000\0" \ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ BOOTENV diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h new file mode 100644 index 00000000000..36f0324902a --- /dev/null +++ b/include/dt-bindings/clock/imx6sx-clock.h @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H +#define __DT_BINDINGS_CLOCK_IMX6SX_H + +#define IMX6SX_CLK_DUMMY 0 +#define IMX6SX_CLK_CKIL 1 +#define IMX6SX_CLK_CKIH 2 +#define IMX6SX_CLK_OSC 3 +#define IMX6SX_CLK_PLL1_SYS 4 +#define IMX6SX_CLK_PLL2_BUS 5 +#define IMX6SX_CLK_PLL3_USB_OTG 6 +#define IMX6SX_CLK_PLL4_AUDIO 7 +#define IMX6SX_CLK_PLL5_VIDEO 8 +#define IMX6SX_CLK_PLL6_ENET 9 +#define IMX6SX_CLK_PLL7_USB_HOST 10 +#define IMX6SX_CLK_USBPHY1 11 +#define IMX6SX_CLK_USBPHY2 12 +#define IMX6SX_CLK_USBPHY1_GATE 13 +#define IMX6SX_CLK_USBPHY2_GATE 14 +#define IMX6SX_CLK_PCIE_REF 15 +#define IMX6SX_CLK_PCIE_REF_125M 16 +#define IMX6SX_CLK_ENET_REF 17 +#define IMX6SX_CLK_PLL2_PFD0 18 +#define IMX6SX_CLK_PLL2_PFD1 19 +#define IMX6SX_CLK_PLL2_PFD2 20 +#define IMX6SX_CLK_PLL2_PFD3 21 +#define IMX6SX_CLK_PLL3_PFD0 22 +#define IMX6SX_CLK_PLL3_PFD1 23 +#define IMX6SX_CLK_PLL3_PFD2 24 +#define IMX6SX_CLK_PLL3_PFD3 25 +#define IMX6SX_CLK_PLL2_198M 26 +#define IMX6SX_CLK_PLL3_120M 27 +#define IMX6SX_CLK_PLL3_80M 28 +#define IMX6SX_CLK_PLL3_60M 29 +#define IMX6SX_CLK_TWD 30 +#define IMX6SX_CLK_PLL4_POST_DIV 31 +#define IMX6SX_CLK_PLL4_AUDIO_DIV 32 +#define IMX6SX_CLK_PLL5_POST_DIV 33 +#define IMX6SX_CLK_PLL5_VIDEO_DIV 34 +#define IMX6SX_CLK_STEP 35 +#define IMX6SX_CLK_PLL1_SW 36 +#define IMX6SX_CLK_OCRAM_SEL 37 +#define IMX6SX_CLK_PERIPH_PRE 38 +#define IMX6SX_CLK_PERIPH2_PRE 39 +#define IMX6SX_CLK_PERIPH_CLK2_SEL 40 +#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41 +#define IMX6SX_CLK_PCIE_AXI_SEL 42 +#define IMX6SX_CLK_GPU_AXI_SEL 43 +#define IMX6SX_CLK_GPU_CORE_SEL 44 +#define IMX6SX_CLK_EIM_SLOW_SEL 45 +#define IMX6SX_CLK_USDHC1_SEL 46 +#define IMX6SX_CLK_USDHC2_SEL 47 +#define IMX6SX_CLK_USDHC3_SEL 48 +#define IMX6SX_CLK_USDHC4_SEL 49 +#define IMX6SX_CLK_SSI1_SEL 50 +#define IMX6SX_CLK_SSI2_SEL 51 +#define IMX6SX_CLK_SSI3_SEL 52 +#define IMX6SX_CLK_QSPI1_SEL 53 +#define IMX6SX_CLK_PERCLK_SEL 54 +#define IMX6SX_CLK_VID_SEL 55 +#define IMX6SX_CLK_ESAI_SEL 56 +#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57 +#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58 +#define IMX6SX_CLK_CAN_SEL 59 +#define IMX6SX_CLK_UART_SEL 60 +#define IMX6SX_CLK_QSPI2_SEL 61 +#define IMX6SX_CLK_LDB_DI1_SEL 62 +#define IMX6SX_CLK_LDB_DI0_SEL 63 +#define IMX6SX_CLK_SPDIF_SEL 64 +#define IMX6SX_CLK_AUDIO_SEL 65 +#define IMX6SX_CLK_ENET_PRE_SEL 66 +#define IMX6SX_CLK_ENET_SEL 67 +#define IMX6SX_CLK_M4_PRE_SEL 68 +#define IMX6SX_CLK_M4_SEL 69 +#define IMX6SX_CLK_ECSPI_SEL 70 +#define IMX6SX_CLK_LCDIF1_PRE_SEL 71 +#define IMX6SX_CLK_LCDIF2_PRE_SEL 72 +#define IMX6SX_CLK_LCDIF1_SEL 73 +#define IMX6SX_CLK_LCDIF2_SEL 74 +#define IMX6SX_CLK_DISPLAY_SEL 75 +#define IMX6SX_CLK_CSI_SEL 76 +#define IMX6SX_CLK_CKO1_SEL 77 +#define IMX6SX_CLK_CKO2_SEL 78 +#define IMX6SX_CLK_CKO 79 +#define IMX6SX_CLK_PERIPH_CLK2 80 +#define IMX6SX_CLK_PERIPH2_CLK2 81 +#define IMX6SX_CLK_IPG 82 +#define IMX6SX_CLK_GPU_CORE_PODF 83 +#define IMX6SX_CLK_GPU_AXI_PODF 84 +#define IMX6SX_CLK_LCDIF1_PODF 85 +#define IMX6SX_CLK_QSPI1_PODF 86 +#define IMX6SX_CLK_EIM_SLOW_PODF 87 +#define IMX6SX_CLK_LCDIF2_PODF 88 +#define IMX6SX_CLK_PERCLK 89 +#define IMX6SX_CLK_VID_PODF 90 +#define IMX6SX_CLK_CAN_PODF 91 +#define IMX6SX_CLK_USDHC1_PODF 92 +#define IMX6SX_CLK_USDHC2_PODF 93 +#define IMX6SX_CLK_USDHC3_PODF 94 +#define IMX6SX_CLK_USDHC4_PODF 95 +#define IMX6SX_CLK_UART_PODF 96 +#define IMX6SX_CLK_ESAI_PRED 97 +#define IMX6SX_CLK_ESAI_PODF 98 +#define IMX6SX_CLK_SSI3_PRED 99 +#define IMX6SX_CLK_SSI3_PODF 100 +#define IMX6SX_CLK_SSI1_PRED 101 +#define IMX6SX_CLK_SSI1_PODF 102 +#define IMX6SX_CLK_QSPI2_PRED 103 +#define IMX6SX_CLK_QSPI2_PODF 104 +#define IMX6SX_CLK_SSI2_PRED 105 +#define IMX6SX_CLK_SSI2_PODF 106 +#define IMX6SX_CLK_SPDIF_PRED 107 +#define IMX6SX_CLK_SPDIF_PODF 108 +#define IMX6SX_CLK_AUDIO_PRED 109 +#define IMX6SX_CLK_AUDIO_PODF 110 +#define IMX6SX_CLK_ENET_PODF 111 +#define IMX6SX_CLK_M4_PODF 112 +#define IMX6SX_CLK_ECSPI_PODF 113 +#define IMX6SX_CLK_LCDIF1_PRED 114 +#define IMX6SX_CLK_LCDIF2_PRED 115 +#define IMX6SX_CLK_DISPLAY_PODF 116 +#define IMX6SX_CLK_CSI_PODF 117 +#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118 +#define IMX6SX_CLK_LDB_DI0_DIV_7 119 +#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120 +#define IMX6SX_CLK_LDB_DI1_DIV_7 121 +#define IMX6SX_CLK_CKO1_PODF 122 +#define IMX6SX_CLK_CKO2_PODF 123 +#define IMX6SX_CLK_PERIPH 124 +#define IMX6SX_CLK_PERIPH2 125 +#define IMX6SX_CLK_OCRAM 126 +#define IMX6SX_CLK_AHB 127 +#define IMX6SX_CLK_MMDC_PODF 128 +#define IMX6SX_CLK_ARM 129 +#define IMX6SX_CLK_AIPS_TZ1 130 +#define IMX6SX_CLK_AIPS_TZ2 131 +#define IMX6SX_CLK_APBH_DMA 132 +#define IMX6SX_CLK_ASRC_GATE 133 +#define IMX6SX_CLK_CAAM_MEM 134 +#define IMX6SX_CLK_CAAM_ACLK 135 +#define IMX6SX_CLK_CAAM_IPG 136 +#define IMX6SX_CLK_CAN1_IPG 137 +#define IMX6SX_CLK_CAN1_SERIAL 138 +#define IMX6SX_CLK_CAN2_IPG 139 +#define IMX6SX_CLK_CAN2_SERIAL 140 +#define IMX6SX_CLK_CPU_DEBUG 141 +#define IMX6SX_CLK_DCIC1 142 +#define IMX6SX_CLK_DCIC2 143 +#define IMX6SX_CLK_AIPS_TZ3 144 +#define IMX6SX_CLK_ECSPI1 145 +#define IMX6SX_CLK_ECSPI2 146 +#define IMX6SX_CLK_ECSPI3 147 +#define IMX6SX_CLK_ECSPI4 148 +#define IMX6SX_CLK_ECSPI5 149 +#define IMX6SX_CLK_EPIT1 150 +#define IMX6SX_CLK_EPIT2 151 +#define IMX6SX_CLK_ESAI_EXTAL 152 +#define IMX6SX_CLK_WAKEUP 153 +#define IMX6SX_CLK_GPT_BUS 154 +#define IMX6SX_CLK_GPT_SERIAL 155 +#define IMX6SX_CLK_GPU 156 +#define IMX6SX_CLK_OCRAM_S 157 +#define IMX6SX_CLK_CANFD 158 +#define IMX6SX_CLK_CSI 159 +#define IMX6SX_CLK_I2C1 160 +#define IMX6SX_CLK_I2C2 161 +#define IMX6SX_CLK_I2C3 162 +#define IMX6SX_CLK_OCOTP 163 +#define IMX6SX_CLK_IOMUXC 164 +#define IMX6SX_CLK_IPMUX1 165 +#define IMX6SX_CLK_IPMUX2 166 +#define IMX6SX_CLK_IPMUX3 167 +#define IMX6SX_CLK_TZASC1 168 +#define IMX6SX_CLK_LCDIF_APB 169 +#define IMX6SX_CLK_PXP_AXI 170 +#define IMX6SX_CLK_M4 171 +#define IMX6SX_CLK_ENET 172 +#define IMX6SX_CLK_DISPLAY_AXI 173 +#define IMX6SX_CLK_LCDIF2_PIX 174 +#define IMX6SX_CLK_LCDIF1_PIX 175 +#define IMX6SX_CLK_LDB_DI0 176 +#define IMX6SX_CLK_QSPI1 177 +#define IMX6SX_CLK_MLB 178 +#define IMX6SX_CLK_MMDC_P0_FAST 179 +#define IMX6SX_CLK_MMDC_P0_IPG 180 +#define IMX6SX_CLK_AXI 181 +#define IMX6SX_CLK_PCIE_AXI 182 +#define IMX6SX_CLK_QSPI2 183 +#define IMX6SX_CLK_PER1_BCH 184 +#define IMX6SX_CLK_PER2_MAIN 185 +#define IMX6SX_CLK_PWM1 186 +#define IMX6SX_CLK_PWM2 187 +#define IMX6SX_CLK_PWM3 188 +#define IMX6SX_CLK_PWM4 189 +#define IMX6SX_CLK_GPMI_BCH_APB 190 +#define IMX6SX_CLK_GPMI_BCH 191 +#define IMX6SX_CLK_GPMI_IO 192 +#define IMX6SX_CLK_GPMI_APB 193 +#define IMX6SX_CLK_ROM 194 +#define IMX6SX_CLK_SDMA 195 +#define IMX6SX_CLK_SPBA 196 +#define IMX6SX_CLK_SPDIF 197 +#define IMX6SX_CLK_SSI1_IPG 198 +#define IMX6SX_CLK_SSI2_IPG 199 +#define IMX6SX_CLK_SSI3_IPG 200 +#define IMX6SX_CLK_SSI1 201 +#define IMX6SX_CLK_SSI2 202 +#define IMX6SX_CLK_SSI3 203 +#define IMX6SX_CLK_UART_IPG 204 +#define IMX6SX_CLK_UART_SERIAL 205 +#define IMX6SX_CLK_SAI1 206 +#define IMX6SX_CLK_SAI2 207 +#define IMX6SX_CLK_USBOH3 208 +#define IMX6SX_CLK_USDHC1 209 +#define IMX6SX_CLK_USDHC2 210 +#define IMX6SX_CLK_USDHC3 211 +#define IMX6SX_CLK_USDHC4 212 +#define IMX6SX_CLK_EIM_SLOW 213 +#define IMX6SX_CLK_PWM8 214 +#define IMX6SX_CLK_VADC 215 +#define IMX6SX_CLK_GIS 216 +#define IMX6SX_CLK_I2C4 217 +#define IMX6SX_CLK_PWM5 218 +#define IMX6SX_CLK_PWM6 219 +#define IMX6SX_CLK_PWM7 220 +#define IMX6SX_CLK_CKO1 221 +#define IMX6SX_CLK_CKO2 222 +#define IMX6SX_CLK_IPP_DI0 223 +#define IMX6SX_CLK_IPP_DI1 224 +#define IMX6SX_CLK_ENET_AHB 225 +#define IMX6SX_CLK_OCRAM_PODF 226 +#define IMX6SX_CLK_GPT_3M 227 +#define IMX6SX_CLK_ENET_PTP 228 +#define IMX6SX_CLK_ENET_PTP_REF 229 +#define IMX6SX_CLK_ENET2_REF 230 +#define IMX6SX_CLK_ENET2_REF_125M 231 +#define IMX6SX_CLK_AUDIO 232 +#define IMX6SX_CLK_LVDS1_SEL 233 +#define IMX6SX_CLK_LVDS1_OUT 234 +#define IMX6SX_CLK_ASRC_IPG 235 +#define IMX6SX_CLK_ASRC_MEM 236 +#define IMX6SX_CLK_SAI1_IPG 237 +#define IMX6SX_CLK_SAI2_IPG 238 +#define IMX6SX_CLK_ESAI_IPG 239 +#define IMX6SX_CLK_ESAI_MEM 240 +#define IMX6SX_CLK_LVDS1_IN 241 +#define IMX6SX_CLK_ANACLK1 242 +#define IMX6SX_PLL1_BYPASS_SRC 243 +#define IMX6SX_PLL2_BYPASS_SRC 244 +#define IMX6SX_PLL3_BYPASS_SRC 245 +#define IMX6SX_PLL4_BYPASS_SRC 246 +#define IMX6SX_PLL5_BYPASS_SRC 247 +#define IMX6SX_PLL6_BYPASS_SRC 248 +#define IMX6SX_PLL7_BYPASS_SRC 249 +#define IMX6SX_CLK_PLL1 250 +#define IMX6SX_CLK_PLL2 251 +#define IMX6SX_CLK_PLL3 252 +#define IMX6SX_CLK_PLL4 253 +#define IMX6SX_CLK_PLL5 254 +#define IMX6SX_CLK_PLL6 255 +#define IMX6SX_CLK_PLL7 256 +#define IMX6SX_PLL1_BYPASS 257 +#define IMX6SX_PLL2_BYPASS 258 +#define IMX6SX_PLL3_BYPASS 259 +#define IMX6SX_PLL4_BYPASS 260 +#define IMX6SX_PLL5_BYPASS 261 +#define IMX6SX_PLL6_BYPASS 262 +#define IMX6SX_PLL7_BYPASS 263 +#define IMX6SX_CLK_SPDIF_GCLK 264 +#define IMX6SX_CLK_CLK_END 265 + +#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ |