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Diffstat (limited to 'src/arm64/qcom/sa8775p.dtsi')
-rw-r--r--src/arm64/qcom/sa8775p.dtsi22
1 files changed, 21 insertions, 1 deletions
diff --git a/src/arm64/qcom/sa8775p.dtsi b/src/arm64/qcom/sa8775p.dtsi
index 231cea1f0fa..1b3dc0ece54 100644
--- a/src/arm64/qcom/sa8775p.dtsi
+++ b/src/arm64/qcom/sa8775p.dtsi
@@ -3605,7 +3605,7 @@
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
pcie0: pcie@1c00000 {
@@ -3677,6 +3677,16 @@
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c04000 {
@@ -3777,6 +3787,16 @@
phy-names = "pciephy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c14000 {