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In some FDTs, there is not enough free memory to add nodes, so this
operation fails.
Signed-off-by: Maxim Moskalets <maximmosk4@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This allows spliting partition list to several lines in environment file
ex:
--------------------
gpt_partition_list=
name=boot1,size=5MiB,start=0x100000;
name=boot2,size=5MiB;
name=rootfs1,size=70MiB;
name=rootfs2,size=70MiB;
name=overlay1,size=20MiB;
name=overlay2,size=20MiB;
name=art,size=4MiB;
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Fixes a compile error when building with only the TCP fastboot
implementation.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240621015135.1570605-1-caleb.connolly@linaro.org
[mkorpershoek: wrapped commit msg to fix checkpatch]
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
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Christian Marangi <ansuelsmth@gmail.com> says:
This is an initial series that have all the initial trivial
fixes required for usage of OF_UPSTREAM for the mediatek SoC
This also contains the pcie-gen3 driver and the required tphy
support driver to make it work.
Subsequent series will follow with conversion of the mtk-clk
to permit usage of OF_UPSTREAM and upstream clk ID.
MT7981, MT7986 and MT7988 migration to upstream clock ID
is complete and working on MT7623.
Series CI tested with PR: https://github.com/u-boot/u-boot/pull/590
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Support alternative compatible for fixed-plls clocks used upstream with
the compatible mediatek,mt7986-apmixedsys.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Support alternative compatible for fixed-plls clocks used upstream with
the compatible mediatek,mt7988-apmixedsys.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Set pcie-phy optional for PCIe gen3. MT7988 doesn't require it and
making it mandatory prevent the driver to correctly probe.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Upstream kernel linux define pinctrl for uart0, hence this pin group
and pinctrl driver is needed before relocation. Add DM_FLAG_PRE_RELOC
flag to init and mute mtk_serial error on early serial init.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Add support for gpio-controller property in root pinctrl node.
This is to follow upstream linux DTSI that doesn't define the
gpio-controller and cells in dedicated nodes.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Support alternative compatible for fixed-plls clocks used upstream with
the compatible mediatek,mt7981-apmixedsys.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Add support for upstream linux clock and map U-Boot property to the one
use in upstream linux where supported.
Also add handling for the use_internal_cd that on upstream is hardcoded
enabled on mt7620.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Upstream linux serial driver use a different logic to setup serial regs.
They have 2 interval:
- < 115200 we use lowspeed regs and 16 * baud
- >= 115200 we use highspeed
We currently use force_highspeed property to force usage of highspeed
regs even with low baud rate.
Add special handling if the upstream compatible is used where we just
apply the same interval with anything >= 115200 in highspeed simulating
force_highspeed.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Upstream linux also provide the additional optional bus clock.
Add support for it and also enable the baud and bus clock on probe.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Add support for optional arb and pmic clock for i2c provided in upstream
linux DTSI.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
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Handle alternative name for pn_swap property as upstream linux use
mediatek,pnswap.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Upstream kernel linux use a different compatible mediatek,spi-ipm.
Add support for this compatible and add handling for the additional
clock similar to how it's done by the upstream driver and handling for
all the property enabled by default.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Add MediaTek GEN3 PCIe controller support for filogic silicon.
This is adapted from the Linux version of the driver.
Signed-off-by: John Crispin <john@phrozen.org>
[ fix minor problems, fix checkpatch errors ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Add support for PHY type switch via the mediatek topmisc syscon.
This is needed on mt7981 to make the PCIe correctly work and display
LinkUp.
Follow the same implementation done on Linux kernel with the usage of
the mediatek,syscon-type property.
Example:
u3port0: usb-phy@11e10700 {
reg = <0x11e10700 0x900>;
clocks = <&topckgen CK_TOP_USB3_PHY_SEL>;
clock-names = "ref";
#phy-cells = <1>;
mediatek,syscon-type = <&topmisc 0x218 0>;
status = "okay";
};
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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There are operations in buildman that result in running the cross-tools
(such as performing size checks) and now that we have not modified PATH
to know where our tools are, these operations fail.
This reverts commit 6c0a3cf75f72370deec3ee516a9dd377397af207.
Signed-off-by: Tom Rini <trini@konsulko.com>
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- Add mvebu_espressobin_ultra-88f3720_defconfig (Benjamin)
- Update DTS for Thecus N2350 board (Tony)
- Add "old" Marvell DDR3 training for Armada 38x and Turris Omnia
(Marek)
- Misc turris_omnia changes (Marek)
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/21504
- Fixes for i.MX8M and i.MX93 clk-composite.
- Set CAN oscillator frequency based on model on verdin-imx8mm.
- Enable CAAM for phycore-imx8mp_defconfig.
- Miscellaneous improvements for Gateworks i.MX8M boards.
- Fix initramfs boot on msc_sm2s_imx8mp.
- Fixe EQoS on imx8mp-beacon-kit.
- Fix error message in fsl_esdhc_imx.
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https://source.denx.de/u-boot/custodians/u-boot-sh
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Currently, Armada 8k config header is setting boot devices and including
<config_distro_bootcmd.h> regardless of the CONFIG_DISTRO_DEFAULTS being
enabled or not, thus populating the environment for distro boot even on
devices that have no need for it.
So, lets simply respect the value of CONFIG_DISTRO_DEFAULTS.
Signed-off-by: Robert Marko <robimarko@gmail.com>
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Support old DDR3 training code on Turris Omnia, selectable via EEPROM
field.
Users experiencing DDR3 initialization failures or random crashes of the
operating system due to incorrect DDR3 configuration can select the old
DDR3 training implementation to fix those issues by setting the EEPROM
field "Use old DDR training":
eeprom update "Use old DDR training" 1
Signed-off-by: Marek Behún <kabel@kernel.org>
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Add optional support for using old DDR3 training code from 2017.
The code lives in drivers/ddr/marvell/a38x/old/. To prevent symbol
clashing with new DDR3 training code, a special header which renames all
clashing symbols via macros is included and the symbols are prefixed
with 'old_'.
If old DDR3 training support is selected for a board, then the SPL
initialization code calls a new function
board_use_old_ddr3_training()
to check whether it should use old DDR3 training code. The default
weak implementation returns false, defaulting to new DDR3 training code.
Boards that wish to support this need to select the
ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
config option and implement the old version of DDR topology provider,
ddr3_get_topology_map().
Signed-off-by: Marek Behún <kabel@kernel.org>
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Backport the option to compile with immutable debug settings also to
the old implementation of the DDR3 training code.
The original PR for mv-ddr-marvell can be seen at
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/45/
Signed-off-by: Marek Behún <kabel@kernel.org>
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Fix some compilation warning in the old DDR training code.
Signed-off-by: Marek Behún <kabel@kernel.org>
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Import DDR training code from commit 1b69ce2fc0ec ("arm: mvebu:
ddr3_debug: remove self assignments") into
drivers/ddr/marvell/a38x/old/. The code is not used yet.
Explanation:
Since 2019, on some Turris Omnia boards we have been having problems
with newer versions of Marvell's DDR3 training code for Armada 38x,
which is ported from mv-ddr-marvell [1] to U-Boot into the
drivers/ddr/marvell/a38x/ directory:
- sometimes the DDR3 training fails on some older boards, sometime it
fails on some newer boards
- other times it succeeds, but some boards experience crashes of the
operating system after running for some time.
Using the stock version of Turris Omnia's U-Boot from solved these
issues, but this solution was not satisfactory, since we wanted
features from new U-Boot.
Back in 2020-2022 we have spent several months trying to debug the
issues, working with Marvell, on our own, and also with U-Boot
community, but these issues persist still.
One solution we used back in 2019 was a "hybrid U-Boot": the SPL part
(containing the DDR3 training code) was taken from the stock version,
while the proper part was current U-Boot at the time. This solution also
has its drawbacks, of which the main one is the need to glue binaries
from two separate builds.
Since then there have been some more changes to the DDR3 training code
in upstream mv-ddr-marvell that have been ported to U-Boot. We have
provided our users experimental builds of U-Boot in the TurrisOS so that
they could try upgrading the firmware and let us know if those problems
still exist. And they do.
We do not have the time nor manpower to debug this problem and fix it
properly. Marvell was also no able to provide a solution to this,
probably because they do not have the manpower as well.
I have therefore come up with this "not that pretty" solution: take the
DDR3 training code from an older version of U-Boot that is known to
work, put it into current U-Boot under old/ subdirectory within
drivers/ddr/marvell/a38x/, build into the SPL binary both the old and
new versions and make it possible to select the old version via an env
variable.
[1] https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell
Signed-off-by: Marek Behún <kabel@kernel.org>
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Some Turris Omnia boards experience memory issues, and by
experimentation we found that some of these issues can be solved by
slowing DDR speed.
Add a new field in the extended EEPROM information structure, ddr_speed.
Support several values in this field (for now 1066F, 1333H, and the
default, 1600K) and use it to overwrite the DDR topology parameters
used by the DDR training algorithm.
Signed-off-by: Marek Behún <kabel@kernel.org>
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Extend the Omnia EEPROM information structure in preparation for more
variables to be stored there.
Signed-off-by: Marek Behún <kabel@kernel.org>
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Enable the 'eeprom' command with support for EEPROM layout for Turris
Omnia. Enable the i2c-eeprom driver so that the EEPROM is accessed via
driver model.
Signed-off-by: Marek Behún <kabel@kernel.org>
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Implement Turris Omnia EEPROM layout for the 'eeprom' command.
When the 'eeprom' command (with layout support) is enabled, we can now
use the 'eeprom print' and 'eeprom update' commands, for example:
=> eeprom print
Magic constant 34a04103
RAM size in GB 2
Wi-Fi Region
CRC32 checksum cecbc2a1
Signed-off-by: Marek Behún <kabel@kernel.org>
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For board revisions where the WAN ethernet PHY reset GPIO is controllable
via MCU we currently insert a phy-reset-gpios property into the ethernet
controller node. The mvneta driver parses this property and uses the
GPIO to reset the PHY.
But this phy-reset-gpios property is not a valid DT binding in upstream
kernel. Instead, a reset-gpios property should be inserted into the
ethernet PHY node. This correct DT binding is supported by the DM ETH PHY
U-Boot driver.
Insert the reset-gpios property into the WAN PHY node instead the
phy-reset-gpios property in WAN ETH node so that Linux will correctly use
the reset GPIO.
Enable the CONFIG_DM_ETH_PHY config option so that U-Boot will also use
the correct DT property.
Note: currently there are 4 ethernet controller drivers parsing the
wrong DT property: dwc_eth_qos, fex_mxc, mvneta and mvpp2. We should
convert all relevant device-trees to use reset-gpios so that we can get
rid of these drivers parsing this property.
Fixes: 1da53ae26afc ("arm: mvebu: turris_omnia: Add support for design with SW reset signals")
Signed-off-by: Marek Behún <kabel@kernel.org>
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by default
Save 10 KiB in Turris Omnia's SPL binary by enabling immutable debug
settings for DDR3 training code.
Signed-off-by: Marek Behún <kabel@kernel.org>
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reduce binary size
Allow compiling with immutable debug settings:
- DEBUG_LEVEL is always set to DEBUG_LEVEL_ERROR
- register dumps are disabled
This can save around 10 KiB of space in the resulting binary, which is a
lot in U-Boot SPL.
Signed-off-by: Marek Behún <kabel@kernel.org>
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and make them static
The variables is_validate_window_per_if, is_validate_window_per_pup,
sweep_cnt and is_run_leveling_sweep_tests are only used if
DDR_VIEWER_TOOL macro is defined, so define them only in that case.
Make them static since they are only used in ddr3_debug.c.
Signed-off-by: Marek Behún <kabel@kernel.org>
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The variables is_default_centralization, is_tune_result and
is_bist_reset_bit are never used.
Signed-off-by: Marek Behún <kabel@kernel.org>
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won't print anything
Return from ddr3_tip_print_log() early if we won't print anything
anyway.
This way the compiler can optimize away the VALIDATE_IF_ACTIVE() calls
in the for-loop, so if the SILENT_LIB macro is defined, no code is
generated for the rest of the function, which saves some space.
Signed-off-by: Marek Behún <kabel@kernel.org>
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Turris Omnia defconfig is nearing image size limit. Disable ext4 write
support to reserve space for more important stuff.
This reduces the size of the KWB image by ~19 KiB.
If in the future U-Boot supports compressing itself and decompressing
on load, we may enable this again.
Signed-off-by: Marek Behún <kabel@kernel.org>
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- Change the spi-max-frequency to 50000000 (50 Mhz). According to the
data sheet[1], the MX25L3205D max frequency is 86 Mhz. Using 50 Mhz in
the DTS to ensure u-boot is consistent with what Linux kernel expected.
- Update GPIO fan to conform to the latest DT binding.
[1]
https://www.macronix.com/Lists/Datasheet/Attachments/8575/MX25L3205D,%203V,%2032Mb,%20v1.5.pdf
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
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The CONFIG_ENV_OFFSET is undefined if boot device is UART
(CONFIG_MVEBU_SPL_BOOT_DEVICE_UART), or envs are not stored on flash
(CONFIG_ENV_IS_NOWHERE). Check for CONFIG_ENV_IS_IN_SPI_FLASH as the first
condition to determine whether env_sf_get_env_addr() should be provided.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
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Add support for a Marvell Armada 3720 device variant
Signed-off-by: Benjamin Schneider <ben@bens.haus>
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Upstream Linux commit f90b68d6c8b0.
The CORE/BUS root slice has following design, simplied graph:
The difference is core not have pre_div block.
A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
It support target(smart) interface and normal interface. Target interface
is exported for programmer easy to configure ccm root. Normal interface
is also exported, but we not use it in our driver, because it will
introduce more complexity compared with target interface.
The normal interface simplified as below:
SEL_A GA
+--+ +-+
| +->+ +------+
CLK[0-7]--->+ | +-+ |
| | | +----v---+ +----+
| +--+ |pre_diva+----> | +---------+
| +--------+ |mux +--+post_div |
| +--+ |pre_divb+--->+ | +---------+
| | | +----^---+ +----+
+--->+ | +-+ |
| +->+ +------+
+--+ +-+
SEL_B GB
The mux in the upper pic is not the target interface MUX, target
interface MUX is hiding SEL_A and SEL_B. When you choose clk[0-7],
you are actually writing SEL_A or SEL_B depends on the internal
counter which will also control the internal "mux".
The target interface simplified as below which is used by Linux Kernel:
CLK[0-7]--->MUX-->Gate-->pre_div-->post_div
A requirement of the Target Interface's software is that the
target clock source is active, it means when setting SEL_A, the
current input clk to SEL_A must be active, same to SEL_B.
We touch target interface, but hardware logic actually also need
configure normal interface.
There will be system hang, when doing the following steps:
The initial state:
SEL_A/SEL_B are both sourcing from clk0, the internal counter
choose SEL_A.
1. switch mux from clk0 to clk1
The hardware logic will choose SEL_B and configure SEL_B to clk1.
SEL_A no changed.
2. gate off clk0
Disable clk0, then the input to SEL_A is off.
3. switch from clk1 to clk2
The hardware logic will choose SEL_A and configure SEL_A to clk2,
however the current SEL_A input clk0 is off, the system hang.
The solution to fix the issue is in step 1, write twice to
target interface MUX, it will make SEL_A/SEL_B both sources
from clk1, then no need to care about the state of clk0. And
finally system performs well.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
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Make public the clk_fetch_parent_index and rename it. This allow
us to be reused in driver specialization
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
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Add missing newline character and also add the return code of
regulator_set_value() to the output.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
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Initialize the Cryptographic Accelerator and Assurance Module.
Signed-off-by: Leonard Anderweit <l.anderweit@phytec.de>
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Since commit ecb1c37a7b64 ("clk: imx8mp: Add EQoS MAC clock"),
the clocks for the DWMAC driver can be configured, and removing
them breaks operation.
Fixes: ecb1c37a7b64 ("clk: imx8mp: Add EQoS MAC clock")
Suggested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Booting an initramfs with the current initrd_addr address may lead to
initramfs corruption and boot failure.
Fix the initramfs problem by applying the following layout
suggested by Tom Rini:
loadaddr=0x40480000 --> Gets moved to 0x40600000 in run-time:
Uncompressing Kernel Image
Moving Image from 0x40480000 to 0x40600000, end=41e80000
fdt_addr_r= moved loadaddr + 128 MiB = 0x48600000
initrd_addr=fdt_addr_r + 512 KiB = 0x48680000
Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
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Synchronize R-Car R8A779G0 V4H PFC tables with Linux 6.9.3,
commit 1b4861e32e461b6fae14dc49ed0f1c7f20af5146 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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