aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2024-04-26rockchip: rk3308: Move cru and grf include files to arch-rockchipJonas Karlman
Move cru_rk3308.h and grf_rk3308.h to arch-rockchip to match path used for all other Rockchip SoCs. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: rk3308-rock-pi-s: Update defconfigJonas Karlman
Update defconfig for rk3308-rock-pi-s with new defaults. Add OF_LIBFDT_OVERLAY=y to support device tree overlays. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Remove BOOTDELAY=0, SYS_CONSOLE_INFO_QUIET=y and enable more CMD to allow use of U-Boot cmdline. Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY. Add PHY_ROCKCHIP_INNO_USB2=y, DM_USB_GADGET=y and remove USB_DWC2=y to allow full use of USB 2.0 host and otg ports. Enable EFI_LOADER to allow EFI boot. Also fix use of USB 2.0 otg port by removing improper use of phy-supply and regulator-always-on props. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: rk3308-roc-cc: Update defconfigJonas Karlman
Update defconfig for rk3308-roc-cc with new defaults. Add OF_LIBFDT_OVERLAY=y to support device tree overlays. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Remove BOOTDELAY=0, SYS_CONSOLE_INFO_QUIET=y and enable more CMD to allow use of U-Boot cmdline. Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY. Add PHY_ROCKCHIP_INNO_USB2=y, DM_USB_GADGET=y and remove USB_DWC2=y to allow full use of USB 2.0 host and otg ports. Enable EFI_LOADER to allow EFI boot. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: rk3308-evb: Update defconfigJonas Karlman
Update defconfig for rk3308-evb with new defaults. Add OF_LIBFDT_OVERLAY=y to support device tree overlays. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Use DEBUG_UART_BASE=0xFF0E0000 and disable DEBUG_UART_BOARD_INIT to make debug uart use uart4, same as stdout-path prop. Remove BOOTDELAY=0, SYS_CONSOLE_INFO_QUIET=y and enable more CMD to allow use of U-Boot cmdline. Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY. Add PHY_ROCKCHIP_INNO_USB2=y, DM_USB_GADGET=y and remove USB_DWC2=y to allow full use of USB 2.0 host and otg ports. Enable EFI_LOADER to allow EFI boot. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: rk3308: Sync device tree from linux v6.8Jonas Karlman
Sync device tree from linux v6.8 and rename the rockchip,rk3308-mac compatible in gmac_rockchip driver to match upstream linux. Also move rk3308-roc-cc gmac node to u-boot.dtsi to not break features not enabled in upstream device tree. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26phy: rockchip-inno-usb2: Add support for RK3308Jonas Karlman
Add clkout_ctl and phy_sus regs to support USB2PHY for RK3308. Based on linux commit 31f840e7ff3e ("phy: phy-rockchip-inno-usb2: add support for RK3308 USB phy"). Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26clk: rockchip: rk3308: Add dummy support for USB480M clockJonas Karlman
Add dummy support for setting parent of USB480M clock. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26clk: rockchip: rk3308: Add support for SCLK_RTC32K clockFinley Xiao
Add support to get and set the SCLK_RTC32K clock rate. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> [jonas@kwiboo.se: Update commit message] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: rk3308: Fix loading FIT from SD-card when booting from eMMCJonas Karlman
When RK3308 boards run SPL from eMMC and fail to load FIT from eMMC due to it being missing or checksum validation fails there can be a fallback to read FIT from SD-card. However, without proper pinctrl configuration reading FIT from SD-card may fail: U-Boot SPL 2024.04-rc4 (Mar 16 2024 - 12:36:12 +0000) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC1 Card did not respond to voltage select! : -110 mmc_init: -95, time 12 spl: mmc init failed with error: -95 Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices (err=-6) ### ERROR ### Please RESET the board ### Fix this by tagging related emmc and sdmmc pinctrl nodes with bootph props. Also sort and move common nodes shared by all boards to the SoC u-boot.dtsi. Imply SPL_PINCTRL and SPL_DM_SEQ_ALIAS to apply correct pinconf before trying to load FIT from a device. Move u-boot,spl-boot-order to soc u-boot.dtsi and define both sdmmc and emmc nodes as fallback. Also fix boot from eMMC (SD NAND) on ROCK Pi S by using correct pinctrl. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: rk3308: Enable random generatorJonas Karlman
The RK3308 SoC contain a crypto engine block that can generate random numbers. Add rng node to soc u-boot.dtsi and enable Kconfig options to take advantage of the random generator. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: rk3308: Generate ethaddr based on cpu idJonas Karlman
Like other Rockchip SoCs the RK3308 has cpu id programmed into OTP memory. The rockchip_otp driver already support the RK3308 variant. However, the device tree is missing a node to enable use of OTP. Add the missing otp node to soc u-boot.dtsi, enable the rockchip_otp driver and enable use of misc_init_r() to set ethaddr based on cpu id. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: rk3308: Enable ARMv8 crypto and FIT checksum validationJonas Karlman
The RK3308 SoC support ARMv8 Cryptography Extensions and use of the ARMv8 crypto extensions help speed up FIT checksum validation in SPL. Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto extensions for SHA256 when validating checksum of FIT images. Imply SPL_FIT_SIGNATURE and LEGACY_IMAGE_FORMAT to enable FIT checksum validation on all RK3308 boards. Also disable CONFIG_SPL_RAW_IMAGE_SUPPORT in board defconfigs to ensure SPL does not try to jump to code that failed checksum validation. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: rk3308: Sort imply statements alphabeticallyJonas Karlman
Sort imply statements under ROCKCHIP_RK3308 alphabetically and remove the config SPL_SERIAL statement from soc Kconfig file, it is already implyed in arch Kconfig. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26board: rockchip: rk3308: Add device tree files and myself to MAINTAINERSJonas Karlman
Update MAINTAINERS files for RK3308 boards to include related device tree files. Also add myself as a reviewer for the ROCK Pi S board. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: spl-boot-order: show DT path for missing deviceChristopher Obbard
When debugging the SPL boot order, the node ID of a device which hasn't been found is printed but it can be quite hard to relate that to the specific devicetree node. To aid debugging, print the node path instead of the cryptic node ID. Original debug message: board_boot_order: could not map node @73c to a boot-device With this patch applied this becomes e.g: board_boot_order: could not map node /spi@ff1d0000/flash@0 to a boot-device Reviewed-by: Dragan Simic <dsimic@manjaro.org> Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-04-26rockchip: spl-boot-order: fix typo in comment succes→successChristopher Obbard
Fix a simple spelling mistake in a comment. Reviewed-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
2024-04-26rockchip: ringneck-px30: put STM32_RST line in input mode instead of outputQuentin Schulz
The STM32_RST line is routed to the ATtiny microcontroller PA0/RESET/UPDI pin. By driving the PX30 SoC pin as GPIO output high, we prevent external UPDI to be used for flashing without first putting this pin as GPIO input, an extra step we could avoid in userspace. There's an external hardware pull-up strong enough to keep the STM32_RST state high on ATtiny side but weak enough it can be overridden by external UPDI. This also means it is safe to use for the STM32 variant, where STM32_RST line will be in the same state as if output high was used. The Q7 standard specifies that MFG_NC1 and MFG_NC2 (used for UPDI for Ringneck) pins should neither be driven by the carrierboard, nor have pull-up or pull-down resistors. This means this commit is safe to use regardless of the carrierboard this module would be connected to (provided it follows the Q7 standard). Fixes: 6acdd63e8771 ("rockchip: ringneck-px30: always reset STM32 companion controller on boot") Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-04-26rockchip: spl: Add SPI NOR flash to boot_devices arrayJonas Karlman
Add missing boot source id <-> device tree node path mapping for SPI NOR flash on PX30, RK3288, RK3308, RK3368 and RV1126. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Dragan Simic <dsimic@manjaro.org>
2024-04-26rockchip: spl: Cache boot source id for later useJonas Karlman
Rockchip BROM writes a boot source id at CFG_IRAM_BASE + 0x10, this id indicates from what storage media TPL/SPL was loaded from. SPL uses this id to determine what device "same-as-spl" represent when determining from where FIT should be loaded. This works as long as the boot_devices array contain a matching id <-> node path entry. However, SPL typically load a small part of TF-A into SRAM and on RK3399 this overwrites the CFG_IRAM_BASE + 0x10 addr used for boot source id. For affected devices the u-boot,spl-boot-device would not be set when booting from SPI flash and the flash@0 node was not explicitly listed in the u-boot,spl-boot-order prop. Here boot source id is 3 before FIT images is loaded, and 0 after: U-Boot SPL 2024.04-rc4 (Mar 15 2024 - 17:26:19 +0000) board_spl_was_booted_from: brom_bootdevice_id 3 maps to '/spi@ff1d0000/flash@0' Trying to boot from SPI ## Checking hash(es) for config config-1 ... OK ## Checking hash(es) for Image atf-1 ... sha256+ OK ## Checking hash(es) for Image u-boot ... sha256+ OK ## Checking hash(es) for Image fdt-1 ... sha256+ OK ## Checking hash(es) for Image atf-2 ... sha256+ OK ## Checking hash(es) for Image atf-3 ... sha256+ OK board_spl_was_booted_from: failed to resolve brom_bootdevice_id 0 spl_decode_boot_device: could not find udevice for /mmc@fe330000 spl_decode_boot_device: could not find udevice for /mmc@fe320000 spl_perform_fixups: could not map boot_device to ofpath: -19 Use a static brom_bootsource_id_cache to save the boot source id after an initial read from SRAM to fix this, this allow spl_perform_fixups() to resolve correct boot source path for "same-as-spl" after SPL have loaded TF-A related FIT images into memory. With this the spl-boot-device prop can correctly be resolved to the SPI flash node in the control FDT: => fdt addr ${fdtcontroladdr} Working FDT set to f1ee6710 => fdt list /chosen chosen { u-boot,spl-boot-device = "/spi@ff1d0000/flash@0"; stdout-path = "serial2:1500000n8"; u-boot,spl-boot-order = "same-as-spl", "/mmc@fe330000", "/mmc@fe320000"; }; Fixes: d57e16c7e712 ("rockchip: find U-boot proper boot device by inverting the logic that sets it") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org>
2024-04-26rockchip: bootrom: Sync bootsource id enum from bootromJason Zhu
Add more bootsource id: 1. BROM_BOOTSOURCE_UNKNOWN 2. BROM_BOOTSOURCE_I2C 3. BROM_BOOTSOURCE_SPI Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> [jonas@kwiboo.se: Update commit message] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Dragan Simic <dsimic@manjaro.org>
2024-04-23Merge tag 'fsl-qoriq-2024-4-24' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq - move to OF_UPSTREAM for sl28
2024-04-23Merge https://source.denx.de/u-boot/custodians/u-boot-snapdragonTom Rini
Support is added for 5 new Qualcomm SoCs: * QCM2290 and SM6115 are low and mid range SoCs used on the RB1 and RB2 respectively. SM6115 is also used in some mid-range smartphones/tablets. Initial support includes buttons and USB (host and gadget). * SM8250 is a flagship SoC from 2020 used on the RB5, as well as many flagship smartphones. The board can boot to a U-Boot prompt, but is missing regulators necessary for USB support. * SM8550, and SM8650 are flagship mobile SoCs from 2023 and 2024 respectively. Found on many high end smartphones. In addition: * Support is added for the Schneider HMIBSC board. * mach-snapdragon switches to OF_UPSTREAM * IPQ40xx gets several regressions fixed and some overall cleanup. * The MSM serial driver gains the ability to generate the bit-clock automatically, no longer relying on a custom DT property. * The Qualcomm SMMU driver gets a generic compatible (so per-SoC compatibles don't need to be added). * Support for the GENI I2C controller is added. * The qcom SPMI driver has SPMI v5 support fixed, and v7 support added. * The qcom sdhci driver gets some fixes for SDCC v5 support. * SDM845 gains sdcard support * Support is added for the Synopsys eUSB2 PHY driver (used on SM8550 and SM8650) * SYS_INIT_SP_BSS_OFFSET is set to 1.5M to give us more space for FDTs. * RB2 gets a work-around to fix the USB dr_mode property before booting Linux.
2024-04-24board: sl28: move to OF_UPSTREAMMichael Walle
Use the new device devicetree files in dts/upstream/ and delete the old ones. Still keep the -u-boot.dtsi with all u-boot specifics around. There is one catch and that is fsl-ls1028a-kontron-sl28-var3.dts which is not available upstream (yet!). For now, the base dts is used for this variant as this only differ in the compatible and the (human readable) model name. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-04-23configs: qcom_defconfig: enable GENI I2C DriverNeil Armstrong
Enable the GENI I2C driver in the default Qualcomm defconfig. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23i2c: Add support for Qualcomm Generic Interface (GENI) I2C controllerNeil Armstrong
Add Support for the Qualcomm Generic Interface (GENI) I2C interface found on newer Qualcomm SoCs. The Generic Interface (GENI) is a firmware based Qualcomm Universal Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple bus protocols depending on the firmware type loaded at early boot time based on system configuration. It also supports the "I2C Master Hub" which is a single function Wrapper that only FIFO mode I2C. It replaces the fixed-function QUP Wrapper found on older SoCs. The geni-se.h containing the generic GENI Serial Engine registers defines is imported from Linux. Only FIFO mode is implemented, neither SE DMA nor GPI DMA are implemented. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23qcom_defconfig: generate SMBIOS tablesCaleb Connolly
EFI initialisation fails without this, and with proper SMBIOS v3 support in (and automatic generation of useful tables) there's no reason for us not to do this on qcom platforms. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23qcom_defconfig: define safe default SYS_LOAD_ADDRCaleb Connolly
Defining this as 0 results in bootm causing a null pointer exception... Define it at a safe default which is valid RAM on most qcom boards. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23qcom_defconfig: enable OF_BOARD_SETUPCaleb Connolly
Use our new ft_board_setup(). Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mach-snapdragon: implement ft_board_setup() for USB role selectionCaleb Connolly
Some Qualcomm boards have only one USB controller which is muxed between the type-c port and an internal USB hub for type-A and ethernet. We modify the DT for these to force them to host mode in U-Boot. However in Linux DRD role switching is supported (required, even). Use ft_board_setup() to adjust the dr_mode property for these boards. While we're here, define pr_fmt for this file so we can more easily identify log messages. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23arm: dts: qrb4210-rb2-u-boot: add u-boot fixupsCaleb Connolly
Add a fixup to force dr_mode to host for U-Boot. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23phy: qcom: snps-femto-v2: drop clocksCaleb Connolly
There is a clock associated with this phy, but it's always from the rpmhcc and isn't actually needed for the hardware to work. Drop all the clock handling from the driver. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23iommu: qcom-smmu: add qcom generic compatibleCaleb Connolly
With the exception of SDM845, most other Qualcomm SoCs have the Qualcomm specific (but not SoC) specific SMMU compatible string. Add it here so we can match those without having to add individual SoCs to the list here. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23gpio: qcom_pmic: add pm8150lCaleb Connolly
This is used for the volume keys on some SM8150/SM8250 devices. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23gpio: qcom_pmic: add pm6125Caleb Connolly
As with some other modern PMICs, writing to the GPIOs seems to make the device reset. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: support controller version 7Neil Armstrong
Add the defines and support for SPMI arbiters version 7, which can handle up to 1024 peripherals, and can also drive a secondary bus which is not implemented yet. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: handle peripheral ownershipNeil Armstrong
The cnfg registers provides the owner id for each peripheral, so we can use this id to check if we're allowed to write register to each peripherals. Since the v5 can handle more peripherals, add the max_channels to scan more starting from version 5, make the channel_map store 32bit values and introduce the SPMI_CHANNEL_READ_ONLY flag to mark a peripheral as read-only. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: properly format commandNeil Armstrong
Since version 2, the cmd format has changed, takes helpers from Linux driver and use a switch/case to handle all versions in msm_spmi_write/read() command. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: fix version 5 supportNeil Armstrong
Properly use ch_offset in msm_spmi_write() reg access. Fixes: f5a2d6b4b03 ("spmi: msm: add arbiter version 5 support") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23board: add support for Schneider HMIBSC boardSumit Garg
Support for Schneider Electric HMIBSC. Features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 2GiB RAM - 64GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI Features enabled in U-Boot: - RAUC updates - Environment protection - USB based ethernet adaptors Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23arm: dts: qcom: Add Schneider HMIBSC board dtsSumit Garg
Schneider HMIBSC board dts has already been reviewed upstream on the linux-arm-msm mailing list. So once it comes through the Linux kernel release cycle into the U-Boot dts/upstream subtree, a switch to OF_UPSTREAM can be made. For the time being maintain the U-Boot copy. Link: https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.garg@linaro.org/ Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: apq8016: Add GPIO pinctrl functionSumit Garg
Add GPIO pinctrl function to enable driving GPIO pins as output low or high. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: Add support for driving GPIO pins outputSumit Garg
Add support for driving the GPIO pins as output low or high. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial_msm: Enable RS232 flow controlSumit Garg
SE HMIBSC board debug console requires RS232 flow control, so enable corresponding support if RS232 gpios are present. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23apq8016: Add support for UART1 clocks and pinmuxSumit Garg
SE HMIBSC board uses UART1 as the main debug console, so add corresponding clocks and pinmux support. Along with that update instructions to enable clocks for debug UART support. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by defaultSumit Garg
Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is loaded as a first stage bootloader. It leads to secondary CPUs bringup failure and later causing the Linux kernel to freeze. So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's actually required. Fixes: 059d526af312 ("mach-snapdragon: generalise board support") Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: ipq4019: support all pin functionsRobert Marko
Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOCRobert Marko
If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTSRobert Marko
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mach-ipq40xx: import GPIO header from mach-snapgradonRobert Marko
Pinctrl driver was refactored and moved, but the required header that it depends on was not included. Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: allow selecting with ARCH_IPQ40XXRobert Marko
IPQ4019 pinctrl driver was moved to the dedicated Qualcomm pinctrl directory, but the KConfig depends on ARCH_SNAPDRAGON only and thus PINCTRL_QCOM_IPQ4019 cannot be selected when ARCH_IPQ40XX is used. Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-13 03:05:07 +0000