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2017-04-24armv8: ls104xardb: Secure Boot: enable PPA support for eMMC/SD and NAND bootSumit Garg
Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: fsl-layerscape: Add validation of PPA image from NAND and SDSumit Garg
Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND FlashSumit Garg
Add Kconfig option to support loading PPA header from eMMC/SD and NAND Flash. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: ls1046aqds: Integrate FSL PPAHou Zhiqiang
The PPA is a EL3 firmware, which support PSCI, hotplug, power-management features etc. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: ls1043aqds: enable FSL PPAHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: ls1043aqds: Integrate FSL PPAHou Zhiqiang
The PPA is a EL3 firmware, which support PSCI, hotplug, power-management features etc. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: ls2080ardb: Add phy number for serdes1 protocol 0x4bSantan Kumar
Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24arm: ls1021atwr: Enable RGMII TX/RX clock internal delay for AR8033Alison Wang
Since commit ce412b7, RGMII TX clock internal delay is not enabled for AR8033 unconditionally. On LS1021ATWR board, the third port eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to be enabled. This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX clock internal delay for AR8033 on the third port. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-18Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-04-18Merge git://git.denx.de/u-boot-x86Tom Rini
2017-04-18Merge branch 'master' of git://git.denx.de/u-boot-ubiTom Rini
2017-04-18board: Remove orphan SPARC boardsTom Rini
Since 936478e797a8 SPARC as been removed as an architecture. Remove these now orphan boards. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-18rockchip: Print a message when returning to the bootromSimon Glass
At present if the return to bootrom fails (e.g. because you are not using the Rockchip's bootrom's pointer table in MMC) then the board prints SPL message and hangs. Print a message first if we can, to help in understanding what happened when it hangs. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Heiko Stuebner <heiko@sntech.de>
2017-04-18drivers/crypto/fsl: remove redundant logical contraintxypron.glpk@gmx.de
'A || (!A && B)' is equivalent to 'A || B'. Let's reduce the complexity of the statement in start_jr0(). The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-18fsl/sata: correctly identify failed mallocxypron.glpk@gmx.de
After allocating sata->cmd_hdr_tbl_offset we have to check this variable and not variable sata. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-18ddr: fsl: incorrect logical constraint in populate_memctl_optionsxypron.glpk@gmx.de
(pdimm[0].data_width >= 32) || (pdimm[0].data_width <= 40) is always true. We should use && here. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-18FPGA: drivers/fpga/ivm_core.c: incorrect printfxypron.glpk@gmx.de
The number of arguments for printf does not match the format string. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-18usbtty: avoid potential NULL pointer dereferencexypron.glpk@gmx.de
If current_urb is NULL it should not be dereferenced. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-18yaffs2: remove redundant conditionxypron.glpk@gmx.de
If !parent, the changed line is not reached. So there is no need to check the value again. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-18tools/env: avoid memory leak in fw_setenvxypron.glpk@gmx.de
If realloc fails we should release the old buffer. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-18arm: omap-common: add missing va_end()xypron.glpk@gmx.de
Each call of va_start must be matched by a call of va_end. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-18travis-ci: Switch over to Linaro gcc-6.3.1 toolchains for ARMTom Rini
Linaro provides a number of pre-built GCC toolchains for both 32 and 64bit ARM. Switch to their 2017.02 release of gcc-6.3.1 for both. Cc: Koen Kooi <koen.kooi@linaro.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-18buildman: Allow 'gnueabihf' toolchains for ARMTom Rini
Many toolchains for ARM use the 'gnueabihf' suffix rather than just 'gnueabi', so allow these to be used, but with a lower priority than 'gnueabi' ones. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-18sysreset: psci: support system reset in a generic way with PSCIMasahiro Yamada
If the system is running PSCI firmware, the System Reset function (func ID: 0x80000009) is supposed to be handled by PSCI, that is, the SoC/board specific reset implementation should be moved to PSCI. U-Boot should call the PSCI service according to the arm-smccc manner. The arm-smccc is supported on ARMv7 or later. Especially, ARMv8 generation SoCs are likely to run ARM Trusted Firmware BL31. In this case, U-Boot is a non-secure world boot loader, so it should not be able to reset the system directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-18ARM: adjust arm-smccc code for use in U-BootMasahiro Yamada
Adjust ARM SMC Calling Convention code for U-Boot: - Replace the license block with SPDX - Change path to asm-offsets.h - Define UNWIND() as no-op - Add Kconfig entry - Add asm-offsets Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-18ARM: import arm-smccc code from Linux 4.11-rc6Masahiro Yamada
Imports ARM SMC Calling Convention code from Linux 4.11-rc6. The files have been copied as follows: [Linux] [U-Boot] arch/arm/kernel/smccc-call.S -> arch/arm/cpu/armv7/smccc-call.S arch/arm64/kernel/smccc-call.S -> arch/arm/cpu/armv8/smccc-call.S arch/arm/include/asm/opcodes* -> arch/arm/include/asm/opcodes* include/linux/arm-smccc.h -> include/linux/arm-smccc.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-18blackfin: ibf-dsp561: remove orphan Blackfin boardMasahiro Yamada
This is a Blackfin board that commit ea3310e8aafa ("Blackfin: Remove") missed to remove. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-18drivers: remove Blackfin specific driversMasahiro Yamada
These drivers have no user since commit ea3310e8aafa ("Blackfin: Remove"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-04-18cmd: remove Blackfin specific commandsMasahiro Yamada
These commands have no user since commit ea3310e8aafa ("Blackfin: Remove"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-18tools: moveconfig: remove GCC prefix of obsolete architectureMasahiro Yamada
Recently, U-Boot removed support for these architectures. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-18cramfs: basic symlink supportTyler Hall
Handle symlinks to files in the current directory. Other cases could be handled with additional code, but this is a start. Add explicit errors for absolute paths and links found in the middle of a path (directories). Other cases like '..' or '.' will result with the file not being found as when those path components are explicitly provided. Add a helper to decompress a null-terminated link name which is shared with cramfs_list_inode. Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
2017-04-18cramfs: block pointers are 32 bitsTyler Hall
Using a variably-sized type is incorrect here since we're reading a fixed file format. Fixes cramfs on 64-bit platforms. Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
2017-04-18cmd: cramfs: use map_sysmem for sandbox supportTyler Hall
As with most other commands, this needs to factor in the sysmem offset in the sandbox or it will try to dereference the simulated physical address directly. Signed-off-by: Tyler Hall <tylerwhall@gmail.com>
2017-04-18x86: config: Enable dhrystone command for linkSimon Glass
Enable this command so we can get an approximate performance measurement. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-04-18x86: Display the SPL banner only onceSimon Glass
At present on a cold reboot we must reset the CPU to get it to full speed. With 64-bit U-Boot this happens in SPL. At present we print the banner before doing this, the end result being that we print the banner twice. Print the banner a little later (after the CPU is ready) to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-04-18x86: Drop leading spaces in cpu_x86_get_desc()Simon Glass
The Intel CPU name can have leading spaces. Remove them since they are not useful. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-04-18cmd: ubi: remove unnecessary logical constraintxypron.glpk@gmx.de
A size_t variable can never be negative. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2017-04-17Prepare v2017.05-rc2Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-17powerpc/board/t1024rdb: enable board-level reset when issuing reset commandShengzhou Liu
As board-specific reset logic, it needs to issue reset signal via CPLD when issuing 'reset' command in u-boot, this patch solves the issue of reset command not working on T1024RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ramRuchika Gupta
For E6500 cores, L2 cache has been used as init_ram. L1 cache is a write through cache on E6500.If lines are not locked in both L1 and L2 caches, crashes are observed during secure boot. This patch locks/ unlocks both L1 and L2 cache to prevent the crash. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8/fsl-layerscape: fdt: avoid incorrect fixing with CONFIG_SYS_CLK_FREQYangbo Lu
Current sysclk fixing would fix all clocks with 'fixed-clock' compatible. This patch is to fix sysclk by path to avoid any incorrect fixing. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groupsAshish kumar
Number of TZASC instances may vary across NXP SoCs. So put TZASC configuration under instance specific defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls2080a: Add serdes2 protocol 0x51 supportSantan Kumar
Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17arm64/ls1046a: Enable ERRATUM_A008850 for ls1046a SoCShengzhou Liu
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls1046aqds: enable ppa in default configtang yuantian
Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv7: ls1021a: Drop macro CONFIG_LS102XAYork Sun
Use CONFIG_ARCH_LS1021A instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls1043a: Drop macro CONFIG_LS1043AYork Sun
Use CONFIG_ARCH_LS1043A instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls2080a: Drop macro CONFIG_LS2080AYork Sun
Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-17arm: ls1046ardb: Add SD secure boot targetRuchika Gupta
- Add SD secure boot target for ls1046ardb. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM (128K) where 32K are reserved for use by boot ROM and 6K for the header. - Reduce the size of CAAM driver for SPL Blobification functions and descriptors, that are not required at the time of SPL are disabled. Further error code conversion to strings is disabled for SPL build. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17arm: ls1043ardb: Add NAND secure boot targetRuchika Gupta
Add NAND secure boot target for ls1043ardb. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - MACRO for CONFIG_BOOTSCRIPT_COPY_RAM is enabled to copy Bootscript from NAND to DDR. Offsets for Bootscript on NAND and DDR have been also defined. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-11 02:44:28 +0000