aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/cpu/armv8/cache_v8.c
AgeCommit message (Expand)Author
2016-03-21arm64: Fix layerscape mmu setupAlexander Graf
2016-03-15arm64: Only allow dcache disabled in SPL buildsAlexander Graf
2016-03-15arm64: Remove non-full-va map codeAlexander Graf
2016-03-15thunderx: Move mmu table into board fileAlexander Graf
2016-03-15arm64: Make full va map code more dynamicAlexander Graf
2016-03-15arm64: Disable TTBR1 maps in EL1Alexander Graf
2016-03-15thunderx: Calculate TCR dynamicallyAlexander Graf
2016-01-19armv8: New MMU setup code allowing to use 48+ bits PA/VASergey Temerkhanov
2015-11-30armv8/layerscape: Update MMU table with execute-never bitsAlison Wang
2015-11-10armv8: allow custom MMU setup routines on ARMv8Stephen Warren
2015-10-15armv8/mmu: Set bits marked RES1 in TCRThierry Reding
2015-09-01armv8: fsl-lsch3: Rewrite MMU translation table entriesAlison Wang
2015-08-12ARM: cache: implement a default weak flush_cache() functionWu, Josh
2015-08-12ARM: cache: add an empty stub function for invalidate/flush dcacheWu, Josh
2015-07-31armv8: caches: Added routine to set non cacheable regionSiva Durga Prasad Paladugu
2015-07-28armv8/cache: Fix page table creationThierry Reding
2015-02-24armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stackYork Sun
2014-07-03ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun
2014-07-03ARMv8: Adjust MMU setupYork Sun
2014-04-07armv8/cache: Change cache invalidate and flush functionYork Sun
2014-04-07armv8/cache: Consolidate setting for MAIR and TCRYork Sun
2014-01-09arm64: core supportDavid Feng
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-11 09:20:03 +0000