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This adds support for the NanoPi R2S from FriendlyArm.
Rockchip RK3328 SoC
1GB DDR4 RAM
Gigabit Ethernet (WAN)
Gigabit Ethernet (USB3) (LAN)
USB 2.0 Host Port
MicroSD slot
Reset button
WAN - LAN - SYS LED
Signed-off-by: David Bauer <mail@david-bauer.net>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
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The rng is embedded in the SoC so enable it in the device tree
universally, the use of it can be controlled by enabling/disabling
at the device config level.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
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Add missing regulator-init-microvolt property to vdd_log regulator.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Add missing regulator-init-microvolt property to vdd_log regulator.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Add missing regulator-init-microvolt property to vdd_center regulator.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0. Formerly the alias spi1
pointed to &spi5, use an alias spi5 for this instead.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
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SPI flash on this board is located on bus 1, default to using bus 1 for
SPI flash on both rk3399-roc-pc and -mezzanine, and stop aliasing it to
bus 0.
Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Suggested-by: Simon Glass <sjg@chromium.org>
Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
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The input system clock for mt7622 timer is 10MHz and can be retrieved
through the clk driver.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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Add low level platform initialization for the AST2600 SoC.
The 2-stage booting with U-Boot SPL are leveraged to support
different booting mode.
However, currently the patch supports only the booting from
memory-mapped SPI flash.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
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AST2600 is the 7th generation of Aspeed SoC designated for
Interated Remote Management Processor.
AST2600 has significant performance improvement by integrating
1.2GHz dual-core ARM Cortex A7 (r0p5) CPU with FPU. Most of the
controllers are also improved with more features and better
performance than preceding AST24xx/AST25xx.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
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AST2600 has 8 watchdog timers including 8 sets of
32-bit decrement counters, based on 1MHz clock.
A 64-bit reset mask is also supported to specify
which controllers should be reset by the WDT reset.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
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AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600.
The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb),
512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
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This patch adds the clock control driver
for the AST2600 SoC.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
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Set environment for Nand flash (U-boot 2020.04):
- add nand flash in the device tree
- add new default configuration file for G3 using parallel Nand
- set nand parameters in presidio_asic.h
Signed-off-by: Kate Liu <kate.liu@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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The pci_mmc.c driver can generate ACPI info and therefore includes
asm/acpi_table.h by proxy. This file does not exist for the ARM
architecture and thus code compilation failed when using this
driver on ARM.
Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
QEMU.
Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com>
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Enable the USB port for MT8516 Pumpkin Board.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
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Add support for USB on mt8516 based SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
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- R-Car pinctrl updates
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Remove the leading "0x" from rpc node to fix the below dtc warning:
Warning (simple_bus_reg): Node /soc/rpc@0xee200000 simple-bus unit
address format error, expected "ee200000"
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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If no need cache support, not build the cache files, such as in SPL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add a return value to noncached_init and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Enable BINMAN when using Arm-Trusted-Firmware (ATF) to
generate FIT images.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
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Add binman node to device tree to generate the FIT image for u-boot
(u-boot.itb) and OS kernel (kernel.itb).
u-boot.itb contains arm trusted firmware (ATF), u-boot proper and
u-boot device tree for ATF u-boot flow.
kernel.itb contains Linux Image and Linux device tree.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
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SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
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These secure register access functions allow U-Boot proper running
at EL2 (non-secure) to access System Manager's secure registers
by calling the ATF's PSCI runtime services (EL3/secure).
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox command helper function which invokes
the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD)
to send mailbox messages to Secure Device Manager (SDM).
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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Override 'lowlevel_init' to make sure secondary CPUs trapped
in ATF instead of SPL. After ATF is initialized, it will signal
the secondary CPUs to jump from SPL to ATF waiting to be 'activated'
by Linux OS via PSCI call.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do nothing for now.
Users are allowed to override this 'weak' function in their
specific board implementation.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Enable logging features for stm32mp15 boards
- Update MAINTAINERS emails for STI and STM32
- Activate OF_LIVE for ST stm32mp15 boards
- Switch to MCO2 for PHY 50 MHz clock for DHCOM boards
- Correction in stm32prog command on uart: always flush DFU on start command
- Update USB-C power detection algorithm on DK boards
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https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- sync amlogic GX & AXG DT to Linux 5.10
- Add new MESON_EE driver support for GXBB & AXG
- Add support for Libretech-CC v2, Wetek Core2, Beelink GT-King/Pro boards
- add driver for TDO tl070wsh30 panel driver
- meson: isolate loading of socinfo
- Add soc_rev to environment
- Enable G12A support for saradc
- Add correct mmcdev on VIM3(L) & Odroid-N2(C4)
- Read MAC from fuses for VIM3 & VIM3L boards
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A previous series already update STMicroelectronics emails maintainers
but some files have been omitted (Makefile, .dts, .dtsi and .rst files).
Update Patrick and my email address with the one dedicated to upstream
activities.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
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Remove the test on data->dfu_seq, because dfu_seq=0 not only when
the DFU is not started (mask with 0xffff). This flush is mandatory
as the final treatment, common with USB, is done in DFU callback.
This patch avoids issue if the received length is a multiple of
the DFU packet.
For example if size of bootfs partition is egual to 0x4000000,
data->dfu_seq=0 at the end of the partition, the flush it not
requested and the phase is not increased in the callback.
U-Boot continue to request the bootfs in the next GetPhase command.
Fixes: 468f0508b58b ("stm32mp: stm32prog: add serial link support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
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The LAN8710i PHY currently uses 50 MHz clock direct from PLL4P.
To permit PLL4P to run at faster frequency, use MCO2 as a divider.
The PLL4P runs at 100 MHz, supplies MCO2 which divides it by 2 to
50MHz, and supplies the PHY with 50 MHz via pin PG2. The feedback
clock are fed back in via pin PA1.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ia9bf7119785d49b633a3ae761c3dc4a30b92628a
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Define LOG_CATEGORY, change pr_debug to dev_dbg and remove "bsec:"
header as it is managed by log macro (dev->name is displayed)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
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Change debug and pr_ macro to log macro.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
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Change debug and pr_ macro to log macro and define LOG_CATEGORY.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
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Remove board_mmc_init function.
It will be probed with driver-model.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- DM support for OMAP PWM backlight
- USB host mode support for AM654
- Minor SPI fixes
- Add support k2g ice board with 1GHz silicon
- Fix GTC programming for K3 devices
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https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features for 2021.04 cycle
This feature set includes the new board SAMA7G5 EK, the new evaluation
kit for Microchip AT91 SAMA7G5 SoC . The current board support includes
two configurations for booting from eMMC (SDMMC0), SD-Card (SDMMC1), and
support for two Ethernet interfaces.
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Add GTC Clock definition as index 0 clock so that we can use the clock
node in the driver later on.
Signed-off-by: Nishanth Menon <nm@ti.com>
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Enabling the domain clock is performed by the sysc interconnect target
module driver during the video device probing.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
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The previous version of am335x-fb.c contained the functionalities of two
drivers that this patch has split. It was a video type driver that used
the same registration compatible string that now registers a panel type
driver. The proof of this is that two compatible strings were referred
to within the same driver.
There are now two drivers, each with its own compatible string,
functions and API.
Furthermore, the panel driver, in addition to decoding the display
timings, is now also able to manage the backlight.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Adding the 'simple-bus' compatible string to the scm_clocks node will
allow its automatic binding.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
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Adding the 'simple-bus' compatible string to the prcm_clocks node will
allow its automatic binding.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
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Up till this commit passing NULL as input parameter was allowed, but not
handled properly. When a NULL parameter was passed to the function a data
abort was raised.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
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