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path: root/arch/riscv/cpu/fu540
AgeCommit message (Expand)Author
2021-05-17riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng
2021-05-14Revert "riscv: cpu: fu740: clear feature disable CSR"Bin Meng
2021-05-05riscv: cpu: fu740: clear feature disable CSRGreen Wan
2021-03-27cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass
2021-02-15Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini
2021-02-03riscv: Adjust board_get_usable_ram_top() for 32-bitBin Meng
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass
2020-11-28riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controllerPragnesh Patel
2020-09-30riscv: Rework riscv timer driver to only support S-modeSean Anderson
2020-08-25riscv: fu540: Use correct API to get L2 cache controller base addressBin Meng
2020-08-14riscv: sifive: fu540: redundant initializationHeinrich Schuchardt
2020-08-14riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC levelBin Meng
2020-08-14riscv: sifive/fu540: spl: Rename soc_spl_init()Bin Meng
2020-07-24env: Enable SPI flash env for SiFive FU540Jagan Teki
2020-07-03riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel
2020-06-04riscv: sifive: fu540: add SPL configurationPragnesh Patel
2020-06-04riscv: cpu: fu540: Add support for cpu fu540Pragnesh Patel