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Author
2021-05-17
riscv: Split SiFive CLINT support between SPL and U-Boot proper
Bin Meng
2021-05-14
Revert "riscv: cpu: fu740: clear feature disable CSR"
Bin Meng
2021-05-05
riscv: cpu: fu740: clear feature disable CSR
Green Wan
2021-03-27
cpu: Rename SPL_CPU_SUPPORT to SPL_CPU
Simon Glass
2021-02-15
Merge branch '2021-02-02-drop-asm_global_data-when-unused'
Tom Rini
2021-02-03
riscv: Adjust board_get_usable_ram_top() for 32-bit
Bin Meng
2021-02-02
common: Drop asm/global_data.h from common header
Simon Glass
2020-11-28
riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller
Pragnesh Patel
2020-09-30
riscv: Rework riscv timer driver to only support S-mode
Sean Anderson
2020-08-25
riscv: fu540: Use correct API to get L2 cache controller base address
Bin Meng
2020-08-14
riscv: sifive: fu540: redundant initialization
Heinrich Schuchardt
2020-08-14
riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level
Bin Meng
2020-08-14
riscv: sifive/fu540: spl: Rename soc_spl_init()
Bin Meng
2020-07-24
env: Enable SPI flash env for SiFive FU540
Jagan Teki
2020-07-03
riscv: sifive: fu540: enable all cache ways from U-Boot proper
Pragnesh Patel
2020-06-04
riscv: sifive: fu540: add SPL configuration
Pragnesh Patel
2020-06-04
riscv: cpu: fu540: Add support for cpu fu540
Pragnesh Patel