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path: root/arch/riscv/cpu/start.S
AgeCommit message (Expand)Author
2022-09-26riscv: Introduce AVAILABLE_HARTSRick Chen
2022-09-26spl: introduce SPL_XIP to configNikita Shubin
2022-08-11riscv: ae350: Fix XIP config boot failureLeo Yu-Chi Liang
2022-08-11riscv: cpu: set gp before board_init_f_init_reserveNikita Shubin
2022-06-06Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.hTom Rini
2021-10-18riscv: Remove OF_PRIOR_STAGE from RISC-V boardsIlias Apalodimas
2021-05-05riscv: cpu: Add callback to init each coreGreen Wan
2020-12-14riscv: fix the wrong swap value registerBrad Kim
2020-09-30riscv: Add some comments to start.SSean Anderson
2020-09-30riscv: Ensure gp is NULL or points to valid dataSean Anderson
2020-09-30riscv: Consolidate fences into AMOs for available_harts_lockSean Anderson
2020-09-30Revert "riscv: Clear pending interrupts before enabling IPIs"Sean Anderson
2020-07-24riscv: Fix linking error when building u-boot-spl with no SMP supportLeo Yu-Chi Liang
2020-07-01riscv: Clear pending interrupts before enabling IPIsSean Anderson
2020-04-23riscv: Provide a mechanism to fix DT for reserved memoryAtish Patra
2020-04-23riscv: Introduce SPL_SMP Kconfig option for U-Boot SPLBin Meng
2020-04-23riscv: Merge unnecessary SMP ifdefs in start.SBin Meng
2020-02-10riscv: Remove unnecessary instructionSean Anderson
2020-01-17common: Move relocate_code() to init.hSimon Glass
2019-12-10riscv: add option to wait for ack from secondary harts in smp functionsLukas Auer
2019-12-10riscv: Fix clear bss loop in the start-up codeRick Chen
2019-09-03riscv: update fix_rela_dynMarcus Comstedt
2019-08-26riscv: support SPL stack and global data relocationLukas Auer
2019-08-26riscv: add SPL supportLukas Auer
2019-08-26riscv: add run mode configuration for SPLLukas Auer
2019-08-15riscv: Access CSRs using CSR numbersBin Meng
2019-05-09riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...Rick Chen
2019-05-09riscv: Introduce CONFIG_XIP to support booting from flashRick Chen
2019-04-08riscv: hang if relocation of secondary harts failsLukas Auer
2019-04-08riscv: do not rely on hart ID passed by previous boot stageLukas Auer
2019-04-08riscv: add support for multi-hart systemsLukas Auer
2019-04-08riscv: save hart ID in register tp instead of s0Lukas Auer
2019-04-08riscv: delay initialization of caches and debug UARTLukas Auer
2018-12-18riscv: Save boot hart id to the global dataBin Meng
2018-12-18riscv: Move trap handler codes to mtrap.SBin Meng
2018-12-05riscv: ax25-ae350: Pass dtb address to u-boot with a1 registerRick Chen
2018-12-05riscv: Add kconfig option to run U-Boot in S-modeAnup Patel
2018-11-26riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen
2018-11-26riscv: save hart ID and device tree passed by prior boot stageLukas Auer
2018-11-26riscv: do not blindly modify the mstatus CSRLukas Auer
2018-11-26riscv: remove unused labels in start.SLukas Auer
2018-11-26Drop CONFIG_INIT_CRITICALBin Meng
2018-11-26riscv: align mtvec on a 4-byte boundaryLukas Auer
2018-11-26riscv: fix inconsistent use of spaces and tabs in start.SLukas Auer
2018-10-03riscv: Make start.S available for all targetsBin Meng