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AgeCommit message (Expand)Author
2023-12-06riscv: binman: fix the load field formatRandolph
2023-12-06riscv: andes: Fix enable register settings of PLICSWYu Chien Peter Lin
2023-12-05riscv: dts: jh7110: Add watchdog device tree nodeChanho Park
2023-11-02riscv: dts: jh7110: Add rng device tree nodeChanho Park
2023-11-02riscv: import read/write_relaxed functionsChanho Park
2023-11-02riscv: allow resume after exceptionHeinrich Schuchardt
2023-11-02riscv: cpu: jh7110: Add gpio helper macrosChanho Park
2023-11-02riscv: Weakly define invalidate_icache_range()Samuel Holland
2023-11-02riscv: Align the trap handler to 64 bytesSamuel Holland
2023-11-02riscv: Sort target configs alphabeticallySamuel Holland
2023-10-30Kconfig: Remove all default n/no optionsMichal Simek
2023-10-24riscv: Remove common.h usageTom Rini
2023-10-22sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6Andre Przywara
2023-10-19riscv: Add Zbb support for building U-BootYu Chien Peter Lin
2023-10-19riscv: dts: binman: add condition for opensbi os bootRandolph
2023-10-19riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbolRandolph
2023-10-19riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategyRandolph
2023-10-19riscv: binman: Fix compilation errorMayuresh Chitale
2023-10-19riscv: remove dram_init_banksize()Heinrich Schuchardt
2023-10-04riscv: andesv5: Prefer using the generic RISC-V timer driver in S-modeYu Chien Peter Lin
2023-10-04configs: andes: add vender prefix for target nameRandolph
2023-10-04riscv: enable CONFIG_DEBUG_UART by defaultHeinrich Schuchardt
2023-10-04riscv: bootstage: correct bootstage_report guardChanho Park
2023-10-02Merge branch 'next'Tom Rini
2023-09-26riscv: set fdtfile on VisionFive 2Heinrich Schuchardt
2023-09-24common: Drop linux/printk.h from common headerSimon Glass
2023-09-22Record the position of the SMBIOS tablesSimon Glass
2023-09-20riscv: dts: starfive: generate u-boot-spl.bin.normal.outHeinrich Schuchardt
2023-09-20riscv: set fdtfile on VisionFive 2Heinrich Schuchardt
2023-09-06riscv: Correct event usage for riscv_cpu_probe/setupTom Rini
2023-09-06riscv: Rework riscv_cpu_probe for current event macrosTom Rini
2023-09-05risc-v: implement DBCN write byteHeinrich Schuchardt
2023-09-05riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INITShengyu Qu
2023-09-05riscv: jh7110: enable riscv,timer in the device treeTorsten Duwe
2023-09-04Merge tag 'v2023.10-rc4' into nextTom Rini
2023-08-31event: Convert existing spy records to simpleSimon Glass
2023-08-22riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callbackChanho Park
2023-08-15common: return type board_get_usable_ram_topHeinrich Schuchardt
2023-08-10riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USEShengyu Qu
2023-08-10riscv: Add SPL_ZERO_MEM_BEFORE_USE implementationShengyu Qu
2023-08-10riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USEShengyu Qu
2023-08-10riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZEMinda Chen
2023-08-10riscv: dts: starfive: Enable pcie0 dts nodeMinda Chen
2023-08-10cmd/sbi: display new extensionsHeinrich Schuchardt
2023-08-02acpi: Add missing RISC-V acpi_table headerHeinrich Schuchardt
2023-08-02riscv: dts: starfive: Enable PCIe host controllerMason Huo
2023-07-24riscv: define a cache line size for the generic CPUHeinrich Schuchardt
2023-07-24riscv: dts: jh7110: Add clock source from PLLXingyu Wu
2023-07-24riscv: dts: jh7110: Add PLL clock controller nodeXingyu Wu
2023-07-24riscv: setup per-hart stack earlierBo Gan