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AgeCommit message (Expand)Author
2020-09-30riscv: Add some comments to start.SSean Anderson
2020-09-30riscv: Ensure gp is NULL or points to valid dataSean Anderson
2020-09-30riscv: Consolidate fences into AMOs for available_harts_lockSean Anderson
2020-09-30riscv: Clear pending IPIs on initializationSean Anderson
2020-09-30riscv: Use a valid bit to ignore already-pending IPIsSean Anderson
2020-09-30riscv: Match memory barriers between send_ipi_many and handle_ipiSean Anderson
2020-09-30Revert "riscv: Clear pending interrupts before enabling IPIs"Sean Anderson
2020-09-30riscv: Update SiFive device tree for new CLINT driverSean Anderson
2020-09-30riscv: Update Kendryte device tree for new CLINT driverSean Anderson
2020-09-30riscv: Rework Sifive CLINT as UCLASS_TIMER driverSean Anderson
2020-09-30riscv: Clean up initialization in Andes PLICSean Anderson
2020-09-30riscv: Rework Andes PLMT as a UCLASS_TIMER driverSean Anderson
2020-09-30riscv: Rework riscv timer driver to only support S-modeSean Anderson
2020-09-22fdtdec: optionally add property no-map to created reserved memory nodeEtienne Carriere
2020-09-14riscv: define function set_gd()Heinrich Schuchardt
2020-08-25cmd: provide command sbiHeinrich Schuchardt
2020-08-25riscv: fix building with CONFIG_SPL_SMP=nHeinrich Schuchardt
2020-08-25riscv: fu540: Use correct API to get L2 cache controller base addressBin Meng
2020-08-14riscv: additional crash informationHeinrich Schuchardt
2020-08-14riscv: sifive: fu540: redundant initializationHeinrich Schuchardt
2020-08-14riscv: remove redundant logical constraint.Heinrich Schuchardt
2020-08-14riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC levelBin Meng
2020-08-14riscv: sifive/fu540: spl: Rename soc_spl_init()Bin Meng
2020-08-14riscv: Call spl_board_init_f() in the generic SPL board_init_f()Bin Meng
2020-08-04sifive: reset: add DM based reset driver for SiFive SoC'sSagar Shrikant Kadam
2020-08-04fu540: dtsi: add reset producer and consumer entriesSagar Shrikant Kadam
2020-07-24riscv: dts: hifive-unleashed-a00: Make memory node available to SPLBin Meng
2020-07-24riscv: Fix linking error when building u-boot-spl with no SMP supportLeo Yu-Chi Liang
2020-07-24Revert "riscv: Allow use of reset drivers"Bin Meng
2020-07-24env: Enable SPI flash env for SiFive FU540Jagan Teki
2020-07-24sifive: fu540: Add Booting from SPIJagan Teki
2020-07-24riscv: Make SiFive HiFive Unleashed board boot againBin Meng
2020-07-06Merge branch 'next'Tom Rini
2020-07-03riscv: use log functions in fdt_fixupHeinrich Schuchardt
2020-07-03riscv: sifive: fu540: enable all cache ways from U-Boot properPragnesh Patel
2020-07-03riscv: Use optimized version of fdtdec_get_addr_size_no_parentAtish Patra
2020-07-03riscv: Do not return error if reserved node already existsAtish Patra
2020-07-03riscv: Do not build reset.c if SYSRESET is onBin Meng
2020-07-02riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATEBin Meng
2020-07-02riscv: Expand the DT size before copy reserved memory nodeBin Meng
2020-07-02riscv: Avoid the reserved memory fixup if src and dst point to the same placeBin Meng
2020-07-02riscv: fu540: dts: Correct reg size of otp and dmc nodesBin Meng
2020-07-02riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc nodeBin Meng
2020-07-01riscv: dts: hifive-unleashed-a00: add cpu aliasesSagar Shrikant Kadam
2020-07-01riscv: Add Sipeed Maix supportSean Anderson
2020-07-01riscv: Add device tree for K210 and Sipeed Maix BitMSean Anderson
2020-07-01riscv: Allow use of reset driversSean Anderson
2020-07-01riscv: Add option to support RISC-V privileged spec 1.9Sean Anderson
2020-07-01riscv: Clean up IPI initialization codeSean Anderson
2020-07-01riscv: Clear pending interrupts before enabling IPIsSean Anderson