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AgeCommit message (Expand)Author
2016-03-17x86: Add basic support for broadwellSimon Glass
2016-03-17x86: Add support for running Intel reference codeSimon Glass
2016-03-17x86: Drop all the old pin configuration codeSimon Glass
2016-03-17x86: Add an ICH6 pin configuration driverSimon Glass
2016-03-17x86: link: Add pin configuration to the device treeSimon Glass
2016-03-17x86: Update microcode for secondary CPUsSimon Glass
2016-03-17x86: ivybridge: Show microcode version for each coreSimon Glass
2016-03-17x86: Record the CPU details when starting each coreSimon Glass
2016-03-17x86: Move common MRC Kconfig options to the common fileSimon Glass
2016-03-17x86: Allow I/O functions to use pointersSimon Glass
2016-03-17x86: Add macros to clear and set I/O bitsSimon Glass
2016-03-17x86: ivybridge: Drop sandybridge_early_init()Simon Glass
2016-03-17x86: Move Intel Management Engine code to a common placeSimon Glass
2016-03-17x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass
2016-03-17x86: Move common CPU code to its own placeSimon Glass
2016-03-17x86: Move common LPC code to its own placeSimon Glass
2016-03-17x86: Add the root-complex block to common intel registersSimon Glass
2016-03-17x86: Create a common header for Intel register accessSimon Glass
2016-03-17x86: Move microcode code to a common locationSimon Glass
2016-03-17x86: Move cache-as-RAM code into a common locationSimon Glass
2016-03-17x86: cpu: Add functions to return the family and steppingSimon Glass
2016-03-17x86: broadwell: Add a few microcode filesSimon Glass
2016-03-17x86: Add comments to the SIPI vectorSimon Glass
2016-03-17x86: Tidy up mp_init to reduce duplicationSimon Glass
2016-03-17x86: Correct duplicate POST valuesSimon Glass
2016-03-17x86: gpio: Correct GPIO setup orderingSimon Glass
2016-03-17x86: dts: link: Add board ID GPIOsSimon Glass
2016-03-17x86: dts: link: Move SPD info into the memory controllerSimon Glass
2016-03-17x86: link: Add required GPIO propertiesSimon Glass
2016-03-17x86: Add some more common MSR indexesSimon Glass
2016-03-17x86: cpu: Make the vendor table constSimon Glass
2016-03-17x86: Support booting SeaBIOSBin Meng
2016-03-17x86: Implement functions for writing coreboot tableBin Meng
2016-03-17x86: Support writing configuration tables in high areaBin Meng
2016-03-17x86: Simplify codes in write_tables()Bin Meng
2016-03-17x86: Change write_acpi_tables() signature a little bitBin Meng
2016-03-17x86: Use a macro for ROM table alignmentBin Meng
2016-03-17x86: Change to use start/end address pair in write_tables()Bin Meng
2016-03-17x86: Clean up coreboot_tables.hBin Meng
2016-03-17x86: Move sysinfo related to sysinfo.hBin Meng
2016-03-17x86: Move asm/arch-coreboot/tables.h to a common placeBin Meng
2016-03-14dm: Use uclass_first_device_err() where it is usefulSimon Glass
2016-02-21x86: Add Intel Cougar Canyon 2 boardBin Meng
2016-02-21x86: ivybridge: bd82x6x: Support FSP enabled configurationBin Meng
2016-02-21x86: fsp: Make sure HOB list is not overwritten by U-BootBin Meng
2016-02-21x86: ivybridge: Add FSP supportBin Meng
2016-02-21x86: fix memalign() parameter orderStephen Warren
2016-02-08Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini
2016-02-06Use correct spelling of "U-Boot"Bin Meng
2016-02-05x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLEBin Meng
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