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2021-12-05ide: Drop unused CONFIG optionsSimon Glass
CONFIG_SYS_ATA_PORT_ADDR is not used in the code anymore. Drop it and use ATA_PORT_ADDR() locally instead. Drop CONFIG_IDE_RESET_ROUTINE and CONFIG_IDE_SWAP_IO which are also unused. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-05Convert CONFIG_KEYBOARD to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_KEYBOARD Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-05Convert CONFIG_SYS_FDT_LOAD_ADDR to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_SYS_FDT_LOAD_ADDR Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-02sandbox: replace putchar(ch) by fputc(ch, stdout)Heinrich Schuchardt
When compiled with -Og for better debugability u-boot ends up in a stack overflow using gcc (Ubuntu 11.2.0-7ubuntu2) 11.2.0 GNU Binutils for Ubuntu 2.37 putchar(ch) is defined as a macro which ends up calling U-Boot's putc() implementation instead of the glibc one, which calls os_putc() ... Let's use fputc(ch, stdout) instead as fputc() does not exist in U-Boot. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-01Convert CONFIG_FSL_DDR_BIST et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_FSL_DDR_BIST CONFIG_FSL_DDR_INTERACTIVE Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-01Convert CONFIG_SYS_BR0_PRELIM et al to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_BR0_PRELIM CONFIG_SYS_OR1_PRELIM CONFIG_SYS_BR1_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR2_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR3_PRELIM CONFIG_SYS_OR3_PRELIM CONFIG_SYS_BR4_PRELIM CONFIG_SYS_OR4_PRELIM CONFIG_SYS_BR5_PRELIM CONFIG_SYS_OR5_PRELIM CONFIG_SYS_BR6_PRELIM CONFIG_SYS_OR6_PRELIM CONFIG_SYS_BR7_PRELIM CONFIG_SYS_OR7_PRELIM This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms that can set these values do so. Add the relevant SYS_BRx_PRELIM_BOOL to platforms that had not been previously migrated. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-30stm32mp1: ram: remove the support of calibration resultPatrick Delaunay
The support of a predefined DDR PHY tuning result is removed for STM32MP1 driver because it is not needed at the supported frequency when built-in calibration is executed. The calibration parameters were provided in the device tree by the optional node "st,phy-cal", activated in ddr helper file by the compilation flag DDR_PHY_CAL_SKIP and filled with values generated by the CubeMX DDR utilities. This patch - updates the binding file to remove "st,phy-cal" support - updates the device trees and remove the associated defines - simplifies the STM32MP1 DDR driver and remove the support of the optional parameter "st,phy-cal" After this patch, the built-in calibration is always executed and the calibration registers are moved in the phy dynamic part; that allows manual tests. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30ARM: dts: stm32: Auto-detect DHSOM with uSD level translatorMarek Vasut
The uSD level translator on DHSOM and Avenger96 are optional, however it is possible to auto-detect it. This is done by setting SD CMD line high, and then testing whether signal level on CK line matches the signal level on CKIN line. If so, the uSD level translator is present, otherwise it is not populated. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30ARM: dts: stm32: Add custom PHY reset bindings on AV96Marek Vasut
The ethernet PHY must be reset on AV96, however DWMAC currently does not support the MDIO-bus PHY GPIO reset bindings and the ethernet MAC PHY reset property is going away on next DT sync. Add PHY specific reset bindings to trigger the PHY reset and fix sporadic ethernet malfunctions, until the next DT sync. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30ARM: dts: stm32: Use lower-case hex for address for stm32429i-eval-u-boot.dtsiPatrice Chotard
Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30ARM: dts: stm32: Use lower-case hex for address for stm32f746g-eval-u-boot.dtsiPatrice Chotard
Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30ARM: dts: stm32: Use lower-case hex for address for stm32f429-disco-u-boot.dtsiPatrice Chotard
Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30ARM: dts: stm32: Use lower-case hex for address for stm32f469-disco-u-boot.dtsiPatrice Chotard
Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30ARM: dts: stm32: Use lower-case hex for address for stm32f7-u-boot.dtsiPatrice Chotard
Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30ARM: dts: stm32: Use lower-case hex for address for stm32746-disco-u-boot.dtsiPatrice Chotard
Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30ARM: dts: stm32: Use lower-case hex for address for stm32f769-disco-u-boot.dtsiPatrice Chotard
Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30ARM: dts: stm32: Use lower-case hex for address for stm32mp15-u-boot.dtsiPatrice Chotard
Replace upper-case hex with lower-case hex for address. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-29Merge tag 'v2022.01-rc3' into nextTom Rini
Prepare v2022.01-rc3 Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-28dm: core: Add tests for stringlist functionsSimon Glass
These functions currently lack tests so add some. The error handling differs betwee livetree and flattree at present, so only check the error codes with livetree. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-28sandbox: Support unmapping a fileSimon Glass
Add the opposite of mapping, so that we can unmap and avoid running out of address space. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-26sandbox: poweroff in efi_system_reset()Heinrich Schuchardt
efi_system_reset() should exit if called with EFI_RESET_SHUTDOWN. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-23arm: dts: ls1021a-tsn: add sja1105 and eth2 bindingsVladimir Oltean
The eth aliases are for correct probing order, so that each Ethernet port will get a predictable MAC address from the environment. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-18arm64: Add missing GD_FLG_SKIP_RELOC handlingMarek Vasut
In case U-Boot enters relocation with GD_FLG_SKIP_RELOC, skip the relocation. The code still has to set up new_gd pointer and new stack pointer. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2021-11-17arm: dts: am642-sk: Add and Enable USB SuperSpeed Host Port in SPLKishon Vijay Abraham I
Add and Enable USB SuperSpeed Host Port in SPL. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-11-17ast2600: spl: Locate load buffer in DRAM spaceChia-Wei Wang
Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for spl_get_load_buffer() to allow generic SPL image loading code (e.g. FIT and Ymodem) to store data in DRAM. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-17ARM: dts: ast2600: Add ACRY to device treeChia-Wei Wang
Add ACRY DTS node and enable it for AST2600 EVB. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-17clk: ast2600: Add RSACLK control for ACRYChia-Wei Wang
Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine of ASPEED AST2600 SoCs. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17ARM: dts: ast2600: Add HACE to device treeJoel Stanley
Add HACE DTS node and enable it for AST2600 EVB. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17clk: ast2600: Add YCLK control for HACEJoel Stanley
Add YCLK enable for HACE, the HW hash engine of ASPEED AST2600 SoCs. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17aspeed: ast2600: Enlarge SRAM sizeChia-Wei Wang
The AST2600 SRAM has been extended to 88KB since A1 chip revision. This patch updates the SRAM size to offer more space for early stack/heap use. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-17rk3399: Don't enable the debug UART if there is no driverSimon Glass
Some boards do not enable SPL_SERIAL so cannot use the debug UART. Add this condition to the code and drop use of the preprocessor while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2021-11-17arm: Init the debug UARTSimon Glass
At present we don't init the debug UART in the generic ARM code, but instead leave it to individual machines to handle. This is not the way it is supposed to work. Add the required init to the crt files. This ensures that the UART is available as early as possible and that the announcement appears when it should, if enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-17pinctrl: Add Apple pinctrl driverMark Kettenis
This driver supports both pin muxing and GPIO support for the pin control logic found on Apple SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2021-11-16Merge branch '2021-11-15-assorted-fixes'Tom Rini
- Rename "tqc" to "tq" and related updates - Assorted minor ARM updates, build updates and documentation updates
2021-11-16Merge tag 'xilinx-for-v2022.01-rc3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.01-rc3 sdhci: - Fix emmc mini case with missing firmware interface zynqmp: - Restore JTAG interface if required - Allow overriding board name - Add support for DLC21 - Fix one fallthrought statement description - Use config macro instead of name duplication - Save multiboot to variable firmware: - Handle ipi_req errors better - Use local buffer in case user doesn't need it instead of NULL/0 location spi: - gqsi: Fix write issue at low frequencies net: - gem: Disable broadcasts
2021-11-15arm: Fix bad memcpy.S str8w macro argument countPierre-Clément Tosi
Remove the extra (empty) argument passed to str8w, causing the following error: <instantiation>:40:47: error: too many positional arguments str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f ^ u-boot/arch/arm/lib/memcpy.S:240:5: note: while in macro instantiation 17: forward_copy_shift pull=16 push=16 ^ Note: no functional change intended. Fixes: d8834a1323af ("arm: Use optimized memcpy and memset from linux") Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
2021-11-15board: tq: fix spelling of "TQ-Systems"Matthias Schiffer
"TQ-Systems" is written with a dash. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2021-11-15board: rename "tqc" vendor to "tq"Matthias Schiffer
The subdivision name "TQ Components" hasn't been in use for a long time. Rename the vendor directory to "tq", which also matches our Device Tree vendor prefix. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2021-11-12Remove CONFIG_SERIAL_MULTITom Rini
This symbol has been functionally dead for a long time. Remove the last and recent re-introductions of setting it, and update the whitelist so it will not be re-introduced again. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-12Convert CONFIG_FSL_LAYERSCAPE to KconfigTom Rini
This converts the following to Kconfig: CONFIG_FSL_LAYERSCAPE Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-11ARM: dts: am335x-chiliboard: add /chosen/tick-timerMarcin Niestroj
Commit 4b2be78ab66c ("time: Fix get_ticks being non-monotonic") has broken boot on chiliboard platform, as it requires '/chosen/tick-timer' in device-tree. This resulted in following panic message: Could not initialize timer (err -19) Provide missing chosen property in device-tree to fix chiliboard support. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2021-11-11Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- device-tree sync-up with Linux for ls1028a - fixes/update in fsl-ddr driver, fsl-validate, lx2162a, fsl-mc, spintable code, configs, qspi node, pci - enable EFI_SET_TIME support in sl28 - powerpc: Drop -mstring
2021-11-10Merge tag 'u-boot-stm32-20211110' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm - DHSOM update: - Remove nWP GPIO hog - Increase SF bus frequency to 50Mhz and enable SFDP - Disable video output for DHSOM - Disable EFI - Enable DFU_MTD support - Create include file for STM32 gpio driver private data - Split board and SOC STM32MP15 configuration - Device tree alignement with v5.15-rc6 for STM32MP15 - Add binman support for STM32MP15x - Normalise newlines for stm32prog - Update OTP shadow registers in SPL
2021-11-10stm32mp15: tidy up #ifdefs in cpu.cPatrick Delaunay
We should avoid #ifdef in C modules and the unused functions are eliminated by the linker. Use the more readable IS_ENABLE() instead. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10stm32mp15: replace CONFIG_TFABOOT when it is possiblePatrick Delaunay
In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC. This patch also simplifies the code in cpu.c, stm32mp1_ram.c and clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and without TFA) is not supported: the associated initialization code is present only in SPL. This cleanup patch is a preliminary step to support SPL load of OP-TEE in secure world, with SPL in secure world and U-Boot in no-secure world. Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10stm32mp15: remove configs dependency on CONFIG_TFABOOTPatrick Delaunay
Remove the dependency on CONFIG_TFABOOT in stm32mp Kconfig - always activate the ARCH config: CONFIG_ARCH_SUPPORT_PSCI and CONFIG_CPU_V7_HAS_NONSEC - CONFIG_ARMV7_NONSEC is deactivated in trusted defconfig - the correct sysreset driver is activated in each defconfig: CONFIG_SYSRESET_PSCI or SYSRESET_SYSCON Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10arm: stm32mp: bsec: Update OTP shadow registers in SPLPatrick Delaunay
Currently the upper OTP (after 57) are shadowed in U-Boot proper, when TFABOOT is not used. This choice cause an issue when U-Boot is not executed after SPL, so this BSEC initialization is moved in SPL and no more executed in U-Boot, so it is still executed only one time. After this patch this BSEC initialization is done in FSBL: SPL or TF-A. To force this initialization in all the case, the probe of the BSEC driver is forced in SPL in the arch st32mp function: spl_board_init(). Even if today BSEC driver is already probed in STM32MP15x clock driver clk_stm32mp1.c because get_cpu_type() is called in stm32mp1_get_max_opp_freq() function. Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10ARM: dts: stm32: Drop nWP GPIO hog on DHSOMMarek Vasut
The nWP GPIO hog was used to unlock the SPI NOR write protect when U-Boot used to operate the SPI NOR in 1-1-1 mode. Now that the SPI NOR is operated in 1-1-4 mode, the hog has adverse effects and causes transfer corruption, since the hogged pin is also the IO2 pin. Remove the hogs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10gpio: stm32: create include file for driver private dataPatrick Delaunay
The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-10arm: dts: stm32mp15: alignment with v5.15-rc6Patrick Delaunay
Device tree alignment with Linux kernel v5.15-rc6 - Set {bitclock,frame}-master phandles on ST DKx - Add coprocessor detach mbox on stm32mp15x-dkx boards - Add coprocessor detach mbox on stm32mp157c-ed1 board Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
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