aboutsummaryrefslogtreecommitdiff
path: root/cpu/mpc8xxx
AgeCommit message (Expand)Author
2009-03-30fsl-ddr: add the DDR3 SPD infrastructureDave Liu
2009-03-30fsl-ddr: Fix two bugs in the ddr infrastructureDave Liu
2009-02-16fsl-ddr: Allow system to boot if we have more than 4G of memoryKumar Gala
2009-02-16fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controllerKumar Gala
2009-01-23fsl-ddr: use the 1T timing as default configurationDave Liu
2009-01-23fsl-ddr: make the self refresh idle threshold configurableDave Liu
2009-01-23fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu
2009-01-23fsl-ddr: update the bit mask for DDR3 controllerDave Liu
2008-12-03fsl ddr skip interleaving if not supported.Ed Swarthout
2008-10-18Add debug information for DDR controller registersHaiying Wang
2008-10-18Check DDR interleaving modeHaiying Wang
2008-10-18Pass dimm parameters to populate populate controller optionsHaiying Wang
2008-10-18Make DDR interleaving mode work correctlyHaiying Wang
2008-10-18rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD
2008-09-13Coding style cleanup, update CHANGELOGWolfgang Denk
2008-09-07Fix compiler warning in mpc8xxx ddr codeKumar Gala
2008-08-27FSL DDR: Add DDR2 DIMM paramter supportKumar Gala
2008-08-27FSL DDR: Add DDR1 DIMM paramter supportKumar Gala
2008-08-27FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-11 05:04:37 +0000