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path: root/drivers/clk/sifive
AgeCommit message (Expand)Author
2021-07-06drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'Green Wan
2021-05-31drivers: clk: add fu740 supportGreen Wan
2021-01-05dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass
2020-10-15clk: sifive: Include device_compat.hSean Anderson
2020-08-04sifive: reset: add DM based reset driver for SiFive SoC'sSagar Shrikant Kadam
2020-08-04fu540: prci: use common reset indexes defined in binding headerSagar Shrikant Kadam
2020-06-04clk: sifive: fu540-prci: Release ethernet clock resetPragnesh Patel
2020-06-04clk: sifive: fu540-prci: Add ddr clock initializationPragnesh Patel
2020-06-04clk: sifive: fu540-prci: Add clock enable and disable opsPragnesh Patel
2020-05-18common: Drop linux/delay.h from common headerSimon Glass
2020-02-05dm: core: Require users of devres to include the headerSimon Glass
2019-07-19clk: sifive: Drop GEMGXL clock driverAnup Patel
2019-07-19clk: sifive: Sync-up main driver with upstream LinuxAnup Patel
2019-07-19clk: sifive: Sync-up DT bindings header with upstream LinuxAnup Patel
2019-07-19clk: sifive: Sync-up WRPLL library with upstream LinuxAnup Patel
2019-07-19clk: sifive: Factor-out PLL library as separate moduleAnup Patel
2019-06-01clk: sifive: Add clock driver for GEMGXL MGMTBin Meng
2019-05-09clk: sifive: fu540-prci: Change include orderJagan Teki
2019-02-27clk: Add SiFive FU540 PRCI clock driverAnup Patel