Age | Commit message (Expand) | Author |
---|---|---|
2020-02-05 | dm: core: Require users of devres to include the header | Simon Glass |
2019-07-19 | clk: sifive: Drop GEMGXL clock driver | Anup Patel |
2019-07-19 | clk: sifive: Sync-up main driver with upstream Linux | Anup Patel |
2019-07-19 | clk: sifive: Sync-up DT bindings header with upstream Linux | Anup Patel |
2019-07-19 | clk: sifive: Sync-up WRPLL library with upstream Linux | Anup Patel |
2019-07-19 | clk: sifive: Factor-out PLL library as separate module | Anup Patel |
2019-06-01 | clk: sifive: Add clock driver for GEMGXL MGMT | Bin Meng |
2019-05-09 | clk: sifive: fu540-prci: Change include order | Jagan Teki |
2019-02-27 | clk: Add SiFive FU540 PRCI clock driver | Anup Patel |