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path: root/drivers/ddr/marvell
AgeCommit message (Expand)Author
2019-04-12arm: mvebu: Add Marvell's integrated CPUsChris Packham
2019-03-19mv_ddr: ddr3: only use active chip-selects when tuning ODTChris Packham
2019-03-19mv_ddr: ddr3: fix tRAS timimg parameterChris Packham
2018-12-09ARM: mvebu: restore license information in mv_ddr_plat.{c,h}Chris Packham
2018-12-08ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02Chris Packham
2018-05-15ARM: mvebu: a38x: Add missing SPDX license identfierChris Packham
2018-05-14ARM: mvebu: a38x: use non-zero size for ddr scrubbingChris Packham
2018-05-14ARM: mvebu: a38x: restore support for setting timingChris Packham
2018-05-14ARM: mvebu: a38x: sync ddr training code with upstreamChris Packham
2018-05-14ARM: mvebu: a38x: remove some unused codeChris Packham
2018-05-14ARM: mvebu: a38x: move sys_env_device_rev_getChris Packham
2018-05-14ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESSChris Packham
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
2018-01-19ddr: marvell: update ddr controller init and freqChris Packham
2018-01-19ddr: marvell: update additional ODT settingChris Packham
2018-01-19ddr: marvell: use correct TREFI valueChris Packham
2018-01-19ddr: marvell: only assert M_ODT[0] on write for a single CSChris Packham
2017-08-13arm: mvebu: ddr3_debug: remove self assignmentsxypron.glpk@gmx.de
2017-08-13arm: mvebu: remove self assignmentxypron.glpk@gmx.de
2017-07-12driver/ddr: Add support for setting timing in hws_topology_mapMarek Behún
2017-06-16treewide: remove unneeded semicolonsMasahiro Yamada
2016-10-06Various, accumulated typos collected from around the tree.Robert P. J. Day
2016-09-23drivers: squash lines for immediate returnMasahiro Yamada
2016-05-20arm: mvebu: a38x: Weed out floating point useMarek Vasut
2016-05-02Fix spelling of "occurred".Vagrant Cascadian
2016-03-24arm: mvebu: Fix ddr3_init() cpu configDirk Eibach
2016-02-06Use correct spelling of "U-Boot"Bin Meng
2016-01-14mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BITPhil Sutter
2016-01-14axp: Fix debugging support in DDR3 write levelingPhil Sutter
2016-01-14arm: mvebu: Make ECC support configurable on Armada XPStefan Roese
2016-01-14arm: mvebu: ddr: Fix compilation warningStefan Roese
2015-11-17arm: mvebu: Fix SAR1_CPU_CORE_MASKDirk Eibach
2015-11-17arm: mvebu: a38x: Remove unsupported topologiesKevin Smith
2015-09-11bitops: introduce BIT() definitionHeiko Schocher
2015-08-17arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese
2015-08-17arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese
2015-07-23arm: mvebu: a38x: Use correct PEX register access macrosStefan Roese
2015-07-23arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdrStefan Roese
2015-07-23arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directoryStefan Roese
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