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path: root/drivers/net/zynq_gem.c
AgeCommit message (Expand)Author
2020-09-23net: gem: Add support for more PHYs on MDIO busMichal Simek
2020-06-24net: gem: Disable PCS autonegotiation in case of fixed-linkMichal Simek
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass
2020-05-18common: Drop log.h from common headerSimon Glass
2020-05-18common: Drop net.h from common headerSimon Glass
2020-04-06net: zynq-gem: Setup and use mdio base separatelyMichal Simek
2020-04-06net: zynq_gem: Add cache flush to zynq_gem_free_pktAshok Reddy Soma
2020-02-28net: zynq: Free allocated buffers in case of errorMichal Simek
2020-02-28net: zynq_gem: Use ulong instead of u32 data typeT Karthik Reddy
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass
2020-02-05dm: core: Require users of devres to include the headerSimon Glass
2020-01-14net: zynq: Add a note about RX_BUF macroMichal Simek
2019-12-02common: Move ARM cache operations out of common.hSimon Glass
2019-10-08net: zynq_gem: Remove check for VersalSiva Durga Prasad Paladugu
2019-10-08net: zynq_gem: Add new versal compatible stringSiva Durga Prasad Paladugu
2019-10-08net: gem: Remove DECLARE_GLOBAL_DATA_PTR from gem driverMichal Simek
2019-04-16net: gem: Remove phy autodetection codeMichal Simek
2019-04-16net: zynq_gem: Modify phy supported features after max-speed was setSiva Durga Prasad Paladugu
2019-01-24zynq-gem: Use appropriate cache flush/invalidate for RX and TXStefan Theil
2018-12-03net: zynq_gem: Add check for 64-bit dma support by hardwareSiva Durga Prasad Paladugu
2018-12-03net: zynq_gem: Added 64-bit addressing supportVipul Kumar
2018-10-16net: gem: Do not setup any clock for Xilinx SoC VersalMichal Simek
2018-09-27net: zynq_gem: Add support for fixed-link phyMichal Simek
2018-09-26net: zynq_gem: Fix reading of max-speed propertySiva Durga Prasad Paladugu
2018-07-26net: zynq_gem: convert to use livetreeSiva Durga Prasad Paladugu
2018-07-26drivers: net: zynq_gem: fix phy dt node settingGrygorii Strashko
2018-07-02net: zynq_gem: Initialize val variable in zynq_gem_miiphy_read()Michal Simek
2018-06-13net: gem: Check return value from memalign/mallocMichal Simek
2018-06-13net: zynq_gem: Initialize phyreg variableMichal Simek
2018-06-13net: zynq_gem: Fix return type for phy...()Michal Simek
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
2018-04-13net: zynq_gem: Use max-speed property from dtSiva Durga Prasad Paladugu
2018-03-23net: zynq_gem: Dont run any phy detection logic for GMII caseSiva Durga Prasad Paladugu
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas
2017-11-29net: zynq_gem: Dont enable SGMII and PCS selectionSiva Durga Prasad Paladugu
2017-06-02net: zynq_gem: Dont flush dummy descriptorsSiva Durga Prasad Paladugu
2017-06-02net: zynq_gem: Use wait_for_bit with non breakableSiva Durga Prasad Paladugu
2017-06-02net: zynq_gem: Do not return -ENOSYS on successOlliver Schinagl
2017-06-01dm: Rename dev_addr..() functionsSimon Glass
2017-03-16Merge tag 'xilinx-for-v2017.05' of git://www.denx.de/git/u-boot-microblazeTom Rini
2017-03-07net: zynq_gem: Fix masking of supported phydev featuresNathan Rossi
2017-02-17zynq: Move zynq to clock frameworkStefan Herbrechtsmeier
2017-02-17net: zynq: Add clk framework support to zynq ethernet driverStefan Herbrechtsmeier
2017-02-17net: zynq: Don't overwrite gem_rclk_ctrl with default valueStefan Herbrechtsmeier
2017-02-08dm: core: Replace of_offset with accessorSimon Glass
2017-01-10net: zynq_gem: Use clock driver for ZynqMPSiva Durga Prasad Paladugu
2017-01-10net: gem: Use wait_for_bit() instead of private mdio_wait()Michal Simek
2016-12-20net: xilinx: Use mdio_register_seq() to support multiple instancesMichal Simek
2016-12-09Revert "Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze"Tom Rini
2016-12-08net: xilinx: Use mdio_register_seq() to support multiple instancesMichal Simek
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