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path: root/drivers/spi/Kconfig
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2024-06-17spi: versal2: Enable spi drivers for Versal Gen 2Michal Simek
Enable and update OSPI/QSPI/GQSPI drivers to support Versal Gen 2 SoCs. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/691782470f56f7d49a3204f6757296f2752d4156.1716994063.git.michal.simek@amd.com
2024-05-02spi: cv1800b: Add spi nor flash controller driver for cv1800b SoCKongyang Liu
Add spi nor flash controller driver for cv1800b SoC Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-04-18spi: mpc8xx: Add GPIO dependencyChristophe Leroy
Since commit 773ad4ebb1d6 ("spi, mpc8xx: Add support for chipselect via GPIO and fixups"), DM_GPIO is required for 8xx SPI. Add the missing dependency to avoid build failures. Fixes: 773ad4ebb1d6 ("spi, mpc8xx: Add support for chipselect via GPIO and fixups") Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-10-30Kconfig: Remove all default n/no optionsMichal Simek
Similar change was done by commit b4c2c151b14b ("Kconfig: Remove all default n/no options") and again sync is required. default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
2023-10-27spi: add support for Amlogic A1 SPI Flash ControllerIgor Prusov
Add A1 SPIFC driver from Linux. Slightly modified to use u-boot driver framework and accommodate to lack of ioread32_rep/iowrite32_rep. Based on Linux version 6.6-rc4 Signed-off-by: Igor Prusov <IVPrusov@sberdevices.ru> Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20231024225140.366571-2-ivprusov@sberdevices.ru Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> [trini: Drop <common.h> as it's not needed]
2023-07-13spi: bcmbca-hsspi: Add driver for newer HSSPI controllerWilliam Zhang
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-07-13spi: bcm63xx-hsspi: Make driver depend on BCMBCA archWilliam Zhang
ARCH_BCMBCA was introduced to cover individual Broadcom broadband SoC for common features and IP blocks. Use this config instead of each chip config as the Kconfig dependency for Broadcom HSSPI driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-06-10mtd: spi: renesas: Enable SPI_FLASH_SFDP_SUPPORTHai Pham
Enable support for parsing and auto discovery of parameters for SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) tables as per JESD216 standard. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Make SFDP the default unconditionally
2023-04-07Merge branch 'master_sh/gen4/initial' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-sh - Initial R-Car Generation 4 support
2023-04-07spi: renesas: Make driver available on R-Car Gen4Marek Vasut
Use CONFIG_RCAR_64 to make the driver available on both R-Car Gen3 and R-Car Gen4. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-04-06spi: Kconfig: add dependency on CONFIG_MPC85xx for FSL_ESPI entryCorentin Guillevic
The Freescale ESPI driver (CONFIG_FSL_ESPI) relies to the MPC85xx platform (PowerPC) through arch/powerpc/include/asm/immap_85xx.h. The driver can't compile on another architecture/platform. Signed-off-by: Corentin Guillevic <corentin.guillevic@smile.fr>
2023-01-26spi: Add Socionext F_OSPI SPI flash controller driverKunihiko Hayashi
Introduce Socionext F_OSPI controller driver. This controller is used to communicate with slave devices such as SPI flash memories. It supports 4 slave devices and up to 8-bit wide bus, but supports master mode only. This driver uses spi-mem framework for SPI flash memory access, and can only operate indirect access mode and single data rate mode. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-12-22sandbox: Finish migration to KconfigTom Rini
Stop using CONFIG_SANDBOX_ARCH and use CONFIG_SANDBOX instead. For the SPI related defines, set them directly in Kconfig. This now empties arch/sandbox/include/asm/config.h. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-03Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
2022-11-03spi: Add Microchip PolarFire SoC QSPI driverPadmarao Begari
Add QSPI driver code for the Microchip PolarFire SoC. This driver supports the QSPI standard, dual and quad mode interfaces. Co-developed-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-02Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi.gitTom Rini
- NPCM PSPI controller (Jim)
2022-10-31arm: bcmbca: replace ARCH_BCM6858 symbols in Kconfig with BCM6858William Zhang
As CONFIG_ARCH_BCM6858 is replaced with CONFIG_BCM6858, update the driver Kconfig to use the new config symbol. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-31arm: bcmbca: replace ARCH_BCM68360 symbols in Kconfig with BCM6856William Zhang
As CONFIG_ARCH_BCM68360 is replaced with CONFIG_BCM6856, update the driver Kconfig to use the new config symbol. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-31arm: bcmbca: replace ARCH_BCM63158 symbols in Kconfig with BCM63158William Zhang
As CONFIG_ARCH_BCM63158 is replaced with CONFIG_BCM63158, update the Kconfig to use the new config symbol. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2022-10-27spi: nuvoton: add NPCM PSPI controller driverJim Liu
Add Nuvoton NPCM BMC Peripheral SPI controller driver. NPCM750 include two general-purpose SPI interface. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-09-26Merge tag 'xilinx-for-v2023.01-rc1-v2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.01-rc1 (round 2) xilinx: - Add support for new Versal NET SOC zynqmp: - Use mdio bus for ethernet phy description - Wire ethernet phy reset via i2c-gpio versal: - Config cleanup
2022-09-26spi: cadence_qspi: Add support for Versal NET platformMichal Simek
Trivial changes to support cadence ospi driver for Versal NET platform. Also avoid ospi flash reset for now. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0789141f432189aab69bc496fe33e0218d1d7510.1663589964.git.michal.simek@amd.com
2022-09-23spi: add support for MediaTek spi-mem controllerWeijie Gao
This patch adds support for spi-mem controller found on newer MediaTek SoCs This controller supports Single/Dual/Quad SPI mode. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
2022-09-13spi-mem: Add dirmap API from LinuxChin-Ting Kuo
This adds the dirmap API originally introduced in Linux commit aa167f3fed0c ("spi: spi-mem: Add a new API to support direct mapping"). This also includes several follow-up patches and fixes. Changes from Linux include: * Added Kconfig option * Changed struct device to struct udevice * Changed struct spi_mem to struct spi_slave This patch is obtained from the following patch https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-3-seanga2@gmail.com/ The corresponding Linux kernel SHA1 is aa167f3fed0c. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2022-09-13spi: aspeed: Add ASPEED SPI controller driverChin-Ting Kuo
Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-07-13spi: add support for MediaTek MT7621 SoCWeijie Gao
This patch makes mt7621_spi driver available for MediaTek MT7621 SoC Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-06-29arm64: versal: Add versal specific cadence ospi driverT Karthik Reddy
Add support for cadence ospi driver for Versal platform. This driver provides support for DMA read operation which utilizes cadence qspi driver. If "cdns,is-dma" DT property is specified use dma for read operation from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in cadence_ospi_versal driver add a weak function defination in cadence_qspi driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-3-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-22spi: gxp_spi: Add GXP SPI controller driverNick Hawkins
The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-05-03spi: npcm-fiu: add NPCM7xx FIU controller driverJim Liu
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master controller driver using SPI-MEM interface. The FIU supports single, dual or quad communication interface. The FIU controller driver provides flash access in UMA(User Mode Access) mode by using an indirect address/data mechanism. the dts node is followed upstream kernel dts name. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [Jagan: fixed the Kconfig, Makefile order] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2022-04-08spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to KconfigTom Rini
This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-02-24driver: spi: add bcm iproc qspi supportRayagonda Kokatanur
IPROC qspi driver supports both BSPI and MSPI modes. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Roman Bacik <roman.bacik@broadcom.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-02-10spi: apple: Add driver for Apple SPI controllerMark Kettenis
Add a driver for the SPI controller integrated on Apple SoCs. This is necessary to support the keyboard on Apple Silicon laopts since their keyboard uses an Apple-specific HID over SPI protocol. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2021-09-13pci: Drop DM_PCISimon Glass
This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-12spi: rockchip_sfc: add support for Rockchip SFCChris Morgan
This patch adds support for the Rockchip serial flash controller found on the PX30 SoC. It should work for versions 3-5 of the SFC IP, however I am only able to test it on v3. This is adapted from the WIP SPI-MEM driver for the SFC on mainline Linux. Note that the main difference between this and earlier versions of the driver is that this one does not support DMA. In testing the performance difference (performing a dual mode read on a 128Mb chip) is negligible. DMA, if used, must also be disabled in SPL mode when using A-TF anyway. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-07-06spi: synquacer: Add HSSPI SPI controller driver for SynQuacerJassi Brar
This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-06-25spi: Add MXIC controller driverZhengxun
Add a driver for Macronix SPI controller IP. This patch referred from linux spi-mxic.c. The difference from the linux version is described here. 1. To adapt uboot spi framework, modify some functions naming. 2. Remove the incompatible functions of Uboot. 3. Add dummy byte recalculattion function to support dummy buswidth not align data buswidth operation.(ex: 1-1-4, 1-1-8) 4. Add Octal mode support. Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [jagan: fixed file permission, comment line, kconfig] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2021-01-29spi: mtk_snor: add support for MTK SPI NOR controllerSkyLake.Huang
This patch adds support for MTK SPI NOR controller, which you can see on mt7622 & mt7629. 1. This controller is designed only for SPI NOR. We can't adjust its bus clock dynamically. Set clock in dts instead. 2. This controller only supports 1-1-1 write mode. 3. Remove mtk_snor_match_read() since upper SPI-MEM layer already handles command. 4. sf read/write/update commands are tested with this driver. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
2021-01-24spi: add spi controller support for MediaTek MT7620 SoCWeijie Gao
This patch adds spi controller support for MediaTek MT7620 SoC. The SPI controller supports two chip selects. These two chip selects are implemented as two separate register groups, but they share the same bus (DI/DO/CLK), only CS pins are dedicated for each register group. Appearently these two register groups cannot operates simulataneously so they are implemented as one controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-12-18spi: ca_sflash: Add CAxxxx SPI Flash ControllerPengpeng Chen
Add SPI Flash controller driver for Cortina Access CAxxxx SoCs Signed-off-by: Pengpeng Chen <pengpeng.chen@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Vignesh R <vigneshr@ti.com> CC: Tom Rini <trini@konsulko.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-22spi: Add Qualcomm QUP SPI controller driverRobert Marko
This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s. Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW. FIFO and Block modes are supported, no support for DMA mode is planned. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-23xilinx: kconfig: Change Kconfig dependencies for Xilinx driversMichal Simek
Zynq/ZynqMP/Versal IPs should be possible to called also from Microblaze in PL and vice versa. That's why change dependencies and do not limit enabling just for some platforms. This is follow up patch based on commit 664e16ce99a0 ("xilinx: kconfig: Change Kconfig dependencies for Xilinx drivers"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-08-03drivers: spi: Add SPI controller driver for OcteonSuneel Garapati
Adds support for SPI controllers found on Octeon II/III and Octeon TX TX2 SoC platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-07-16spi: fsl_qspi: Support to use full AHB space on i.MXYe Li
i.MX platforms provide large AHB mapped space for QSPI, each controller has 256MB. However, current driver only maps small size (AHB buffer size) of AHB space, this implementation causes i.MX failed to boot M4 with QSPI XIP image. Add config CONFIG_FSL_QSPI_AHB_FULL_MAP (default enabled for i.MX) to address above problem. When the config is set: 1. Full AHB space is divided to each CS. 2. A dedicated LUT entry is used for AHB read only. 3. The MODE instruction in LUT is replaced to standard ADDR instruction 4. The address in spi_mem_op is used to SFAR and AHB read Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
2020-07-10spi: kirkwood: Drop nondm codeBhargav Shah
Drop the nondm code from kirkwood_spi.c since there is no board or any other code using for it. Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09spi: omap3: Drop nondm codeJagan Teki
Now all boards are using this omap3 spi driver in dm model, so drop the nondm code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-11spi: davinci: Drop non-dm codeJagan Teki
Now all boards which are using davinci SPI driver have moved to SPL_DM so drop the unneeded non-dm code. Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
2020-06-11spi: Zap SOFT_SPI (non-dm)Jagan Teki
- Deadline for DM migration already passed by months. - Sent couple of zap patches and - No response on dm conversation hence removed the driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-06-11spi: mxs: Drop nondm codeJagan Teki
Deadline for DM migration already passed by months and no response on full dm conversation hence removed the nondm code. Note: Look like there is no user for nondm code for this driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01spi: Zap sh_spi driverJagan Teki
sh_spi driver is deprecated, no active updates and no board user, hence dropped the same. Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01spi: Kconfig: Move MSCC_BB_SPI, FSL_QSPI into DM_SPIJagan Teki
- MSCC_BB_SPI - FSL_QSPI Both are fully dm-driven, let's move them into DM_SPI side definition. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-14 17:51:53 +0000