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2020-05-11gpio: emulate open drain & open source in dm_gpio_set_value()Neil Armstrong
Handle the GPIOD_OPEN_DRAIN & GPIOD_OPEN_SOURCE flags to emulate open drain and open source by setting the GPIO line as input depending on the requested value. The behaviour is taken from the Linux gpiolib. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-08sata: dwc_ahsata: Fix memory issue in reset_sataYe Li
The reset_sata should reset the sata device info and free the probe_ent memory. Otherwise, it will cause memory leak if we init the sata again. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-08sata: dwc_ahsata: Fix incorrect freeYe Li
Fix coverity issue CID 43665: Free of address-of expression (BAD_FREE) incorrect_free: free frees incorrect pointer pp. pp points the port array field of struct ahci_uc_priv, should not free it. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-08sata: ahsata: Fix wrong operand for checking SERR DIAG_XYe Li
Fix coverity issue CID 3261683: Wrong operator used (CONSTANT_EXPRESSION_RESULT) operator_confusion: ({...; __v;}) | 67108864 is always 1/true regardless of the values of its operand. This occurs as the logical operand of ! When DIAG_X is set, the PHY COMINIT signal is detected, so should use '&' to check whether it is set. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-08sata: ahsata: Fix resource leakYe Li
Fix coverity issue CID 3606684: Resource leak (RESOURCE_LEAK) leaked_storage: Variable uc_priv going out of scope leaks the storage it points to Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-08configs: migrate CONFIG_SYS_MTDPARTS_RUNTIME to defconfigsPatrick Delaunay
Move CONFIG_SYS_MTDPARTS_RUNTIME into Kconfig done by moveconfig.py. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-08configs: migrate CONFIG_SET_DFU_ALT_INFO to defconfigsPatrick Delaunay
Move CONFIG_SET_DFU_ALT_INFO into Kconfig done by moveconfig.py. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-05-07phy: atheros: consolidate {ar8031|ar8035}_config()Michael Walle
The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: ar8035: remove static clock configMichael Walle
We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: add device tree bindings and configMichael Walle
Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: move delay config to common functionMichael Walle
Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: introduce debug read and write functionsMichael Walle
Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: use defines for PHY IDsMichael Walle
Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: fix AR8021 PHY ID maskMichael Walle
The upper bits are all the OUI. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: Clarify the intention of ar8021_configVladimir Oltean
Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at the other bit positions, just like the other PHYs in the family do. Therefore, it is not necessary to hardcode the reserved values, but instead simply follow the read-modify-write procedure from the common function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: Explicitly disable RGMII delaysVladimir Oltean
To eliminate any doubts about the out-of-reset value of the PHY, that the driver previously relied on. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: Clarify the configuration of the CLK_25M output pinVladimir Oltean
Also take the opportunity to use the phy_read_mmd and phy_write_mmd convenience functions. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: Use common functions for RGMII internal delaysVladimir Oltean
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07phy: atheros: Make RGMII Tx delays actually configurable for AR8035Vladimir Oltean
Delete the extraneous write to debug reg 5 that enables Tx delay When the driver was originally introduced in commit "6027384a phylib: Add Atheros AR8035 GETH PHY support", the Tx delay was being unconditionally enabled. Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID", the author did not notice that code for enabling Tx delay code was already. Therefore, the if condition for Tx delay has always been useless for this PHY since this commit introduced it. Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled. After this patch, only those who define the interface as RGMII_TXID or RGMII_ID will. This is to be expected, but will nonetheless break the setups of those who didn't know they rely on Tx delay implicitly. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-05-07uart: pl011: Add proper DM clock supportAndre Przywara
Even though the PL011 UART driver claims to be DM compliant, it does not really a good job with parsing DT nodes. U-Boot seems to adhere to a non-standard binding, either requiring to have a "skip-init" property in the node, or to have an extra "clock" property holding the base *frequency* value for the baud rate generator. DTs in the U-Boot tree seem to have been hacked to match this requirement. The official binding does not mention any of these properties, instead recommends a standard "clocks" property to point to the baud base clock. Some boards use simple "fixed-clock" providers, which U-Boot readily supports, so let's add some simple DM clock code to the PL011 driver to learn the rate of the first clock, as described by the official binding. These clock nodes seem to be not ready very early in the boot process, so provide a fallback value, by re-using the already existing CONFIG_PL011_CLOCK variable. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [trini: Add <clock_legacy.h> for get_bus_freq() for layerscape platforms] Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-06cache: l2x0: Fix missing write to Auxiliary Control RegisterLey Foon Tan
In commit f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") we removed writel to regs->pl310_aux_ctrl by accident. This commit restores it back. Fixes: f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-05-05Merge git://git.denx.de/u-boot-usbTom Rini
- MediaTek USB host support
2020-05-05Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini
- Add DM model for P1010RDB - Add I2C DM Model support for P1010RDB, T1042RDB, T2080, T4240RDB, MPC8548CDS, T1024RDB, P4080, P3041DS, P2041RDB, P2020RDB, P1020RDB, P5040DS - Fix reference to READM.qe_firmware
2020-05-04Merge tag 'u-boot-imx-20200502' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2020.07 ---------------- - imxrt: fix LCD clock, fix doc - new board: Coral Dev - imx8: enable Cache in SPL. SNVS, update SCFW API - imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading - MX6ULL : is_imx6ull to include i.MX6ULZ - Net: add config to enable TXC delay Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
2020-05-04net: pcnet: fix I/O primitives for memory accessDaniel Schwierzeck
Commit 69529c912059 ("net: pcnet: Switch to PCI memory access") switched from PCI IO access to PCI memory access without updating the I/O primitives. Contrary to SH, the primitives for memory access and IO access are implemented differently. Thus doing memory access with IO port primitives breaks the driver on MIPS Malta board. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-05-04Merge tag 'u-boot-rockchip-20200501' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - dts clean up to use -u-boot for px30, rk3399 boards - dts sycn from upstream kernel for rk3328, rk3399 - add rockchip rng driver - new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB
2020-05-04Merge branch 'next' of git://git.denx.de/u-boot-shTom Rini
This is part 1 of big network cleanup / DM conversion. The dc2114x/rtl8139/pcnet/tulip PCI adapter drivers received checkpatch cleanups in preparation for DM conversion. The smc911x is converted to DM completely. The dwc_eth_qos cache fixes are applied.
2020-05-04doc: fix references to README.qe_firmwareHeinrich Schuchardt
In two files README.qe_firmware is referenced which never made it into the U-Boot tree. The README is available in the Linux kernel tree. Update the references. Cc: Timur Tabi <timur@kernel.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04rtc: pt7c4338: Add driver model supportBiwen Li
Add support of driver model of pt7c4338 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04rtc: ds1337: Add driver model supportBiwen Li
Add support of driver model of ds1337 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-02xhci: mediatek: Add support for MTK xHCI host controllerChunfeng Yun
This patch is used to support the on-chip xHCI controller on MediaTek SoCs, currently control/bulk/interrupt transfers are supported. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-02phy: phy-mtk-tphy: add a new reference clockChunfeng Yun
Usually the digital and analog phys use the same reference clock, but some platforms have two separate reference clocks for each of them, so add another optional clock to support them. In order to keep the clock names consistent with PHY IP's, change the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-05-02phy: phy-mtk-tphy: add support new versionChunfeng Yun
The new version removes all shared banks between multi-phys Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-05-02phy: phy-mtk-tphy: add support USB physChunfeng Yun
Support USB2 and USB3 PHY with shared banks when support multi-phys Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-05-02usb: dwc2_udc_otg: use the phy bulk API to get physChunfeng Yun
Use the phy bulk API to get a group of phys Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-05-02usb: dwc3: use the phy bulk API to get physChunfeng Yun
Get a group of phys by the phy bulk API Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-05-02phy: Add API for a bulk of physChunfeng Yun
This patch adds a "bulk" API to the phy API in order to get/init/exit/power on/off a group of phys associated with a device. The bulk API will avoid adding a copy of the same code to manage a group of phys in drivers. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-02dm: core: Add function to get child count of ofnode or deviceChunfeng Yun
This patch add function used to get the child count of a ofnode or a device Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-01clk: imx: clk-imxrt1050: fix lcdif clock gateGiulio Benetti
LCDIF clock gate was wrong so set it according to RM. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-05-01video: mxsfb: add clk_enable()Giulio Benetti
BROM doesn't enable lcdif by default so add clk_enable() after clk_set_rate(). Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-05-01watchdog MediaTek add upstream compatibleMatthias Brugger
The upstream compatible is called mt6589-wdt. Add this compatible to the driver. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-01timer MediaTek use upstream compatibleMatthias Brugger
The timers compatible string in upstream is called mt6577-timer. Add this compatible to the driver. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-01rtc: pcf2127: don't add/subtract 1 to tm_monRasmus Villemoes
As noted in rtc_def.h, the tm_mon field in struct rtc_time is 1-12, unlike in struct tm where it is 0-11. Currently, running "date" prints the wrong Date: 2020-04-01 (Friday) Time: 13:05:30 and setting the RTC via the date command is also broken. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-05-01net: smc911x: Add DM supportMarek Vasut
Add support for U-Boot DM and DT probing. Furthermore, build the SMC911x standalone EEPROM example only for the non-DM case, as it is not converted yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-01net: fec: Add possibility to enable TXC delayPhilippe Schenker
This patch enables the possibility to set FEC_ENET_ENABLE_TXC_DELAY or FEC_ENET_ENABLE_RXC_DELAY so one can via a define enable the RXC or TXC delay in the MAC. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-05-01net: phy: micrel: Add basic support for KSZ9131Philippe Schenker
This adds basic support for the new Micrel KSZ9131 phy. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-05-01net: phy: micrel: Use defines for PHY_IDs and MASKPhilippe Schenker
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
2020-05-01imx8: Configure SNVSFranck LENORMAND
Add a module to configure the tamper and secure violation of the SNVS using the SCU API. The module also adds some commands: - snvs_cfg: Configure the SNVS HP and LP registers - snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP) - tamper_pin_cfg: Change the configuration of the tamper pins - snvs_clear_status: Allow to write to LPSR and LPTDSR to clear status bits Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8: Update SCFW API to version 1.5Ye Li
Sync the latest SCFW API with below commit 6dcd0242ae7a53ac ("SCF-105: Revert accidental change") to add interfaces for PM resource reset and read/write SNVS security violation and tamper DGO registers. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01imx8: scu api: Add support for SECO manufacturing protection APIsBreno Lima
SECO provides APIs to support CAAM manufacturing protection: - sc_seco_get_mp_key() - sc_seco_get_mp_sign() - sc_seco_update_mpmr() Add SCFW APIs support. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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