aboutsummaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2020-01-07dm: core: Use assert_noisy() in devresSimon Glass
Use this macros instead of the linux ones, as the output is smaller. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-07virtio: rng: Add a random number generator(rng) driverSughosh Ganu
Add a driver for the virtio-rng device on the qemu platform. The device uses pci as a transport medium. The driver can be enabled with the following configs CONFIG_VIRTIO CONFIG_DM_RNG CONFIG_VIRTIO_PCI CONFIG_VIRTIO_RNG Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2020-01-07sandbox: rng: Add a random number generator(rng) driverSughosh Ganu
Add a sandbox driver for random number generation. Mostly aimed at providing a unit test for rng uclass. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07stm32mp1: rng: Add a driver for random number generator(rng) deviceSughosh Ganu
Add a driver for the rng device found on stm32mp1 platforms. The driver provides a routine for reading the random number seed from the hardware device. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com> Remove a superfluous blank line Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-01-07clk: stm32mp1: Add a clock entry for RNG1 deviceSughosh Ganu
Add an entry for allowing clock enablement for the random number generator peripheral, RNG1. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07dm: rng: Add random number generator(rng) uclassSughosh Ganu
Add a uclass for reading a random number seed from a random number generator device. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07power: regulator: support off-on-delay-usPeng Fan
off-on-delay-us has been supported by Linux, so let's use it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-01-07remoteproc: stm32: load resource table from firmwareFabien Dessenne
Load the optional resource table from the firmware, and write its address in the dedicated backup register. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07remoteproc: stm32: track the coprocessor state in a backup registerFabien Dessenne
Update the dedicated backup register to track the coprocessor state and rely on that register to compute the .is_running() value (which expects a return value of 0 -not 1- if the processor is running). Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-01-07remoteproc: elf_loader: Add elf resource table load supportFabien Dessenne
Add rproc_elf_load_rsc_table(), which searches for a resource table in an elf64/elf32 image, and if found, copies it to device memory. Add also the elf32 and elf64 variants of this API. Add a test for this. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-07drivers: board: Add get_fit_loadable()Jean-Jacques Hiblot
This function will be used by the SPL to get the names of images to load from the FIT. This allows to load different images based on runtime HW detection. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07drivers: board: Make the board drivers available in SPLJean-Jacques Hiblot
Make the board driver available in the SPL too. The board driver is a way to provide useful information about the board and that can be useful in the SPL too. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-01-07Merge tag 'u-boot-imx-20200107' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx New for 2020.04 --------------- - New boards Embedded Artists COM board Xea Board - Switch to DM: Aristainetos boards Toradex colibri (DM_ETH) iCubox GE bx50v3 mx7dsabre (DM_ETH) cx9020 - New features: Bootaux with elf files Default SYS_THUMB_BUILD for i.MX6/7 - Fixes: DHCOM i.MX6 PDK Engicam i.MX8M tools (imx8m_image) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
2020-01-07Merge tag 'u-boot-atmel-2020.04-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel features for 2020.04 cycle This feature set is a patch series from Tudor Ambarus which includes parsing of the spi flash SFDP parser for SST flashes, and using those tables to retrieve unique saved per device MAC address. This is then used as base mac address on the SAMA5D2 Wireless SOM EK board.
2020-01-07ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC AccessThor Thayer
The ECC registers in the SDRAM HMC Adapter should always be accessible (both when ECC is enabled and disabled). Currently, the registers are accessible only when ECC is enabled. The ECC Enabled bit is used to determine the status of ECC by later OSes so always allow access. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-01-07arm: socfpga: stratix10: Enable SMMU accessThor Thayer
Enable TCU access through the Stratix10 CCU so that the SMMU can access the SDRAM. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-01-07ddr: altera: agilex: Add SDRAM driver for AgilexLey Foon Tan
Add SDRAM driver for Agilex SoC. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07ddr: altera: Restructure Stratix 10 SDRAM driverLey Foon Tan
Restructure Stratix 10 SDRAM driver. Move common code to separate file, in preparation to support SDRAM driver for Agilex. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07cache: Add Arteris Ncore cache coherent unit driverLey Foon Tan
Add Cache Coherency Unit (CCU) driver. CCU is to ensures consistency of shared data between multi masters in the system. Driver initializes CCU's directories and coherency agent interfaces in CCU IP. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07clk: agilex: Add clock driver for AgilexLey Foon Tan
Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan
Move Stratix10 and Agilex system manager common code to system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Move firewall code to firewall fileLey Foon Tan
Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert clock manager from struct to definesLey Foon Tan
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get clock manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert system manager from struct to definesLey Foon Tan
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: Convert reset manager from struct to definesLey Foon Tan
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07spl: Allow cache drivers to be used in SPLLey Foon Tan
Add an option for building cache drivers in SPL. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07dfu: Add optional timeout parameterAndy Shevchenko
When the `dfu` command is called from the U-Boot environment, it now accepts an optional parameter that specifies a timeout (in seconds). If a DFU connection is not made within that time the `dfu` command exits (as it would if Ctrl+C was pressed). If the timeout is left empty or being zero the `dfu` command behaves as it does now. This is useful for allowing U-Boot to check to see if anything wants to upload new firmware before continuing to boot. The patch is based on the commit https://github.com/01org/edison-u-boot/commit/5e966ccc3c65c18c9783741fa04e0c45e021780c by Sebastien Colleur, which has been heavily reworked due to U-Boot changes in the past. Signed-off-by: Brad Campbell <bradjc5@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-01-07video: meson: Drop unnecessary header includesSimon Glass
These files should not be included in meson header files. Drop them and tidy up the affected C files. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-01-07ddr: imx8m: Return error values from LPDDR4 trainingFrieder Schrempf
In cases when the same SPL should run on boards with i.MX8MM, that differ in DDR configuration, it is necessary to try different parameters and check if the training done by the firmware suceeds or not. Therefore we return the DDR training/initialization success to the upper layer in order to be able to retry with different settings if necessary. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2020-01-07pci: imx: Add iMX6SX compatibleMarek Vasut
The driver works fine with iMX6SX, add the missing compatible string. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2020-01-07video: lg4573: convert to DMHeiko Schocher
convert this driver to support DM. Signed-off-by: Heiko Schocher <hs@denx.de>
2020-01-06Merge branch 'next'Tom Rini
Bring in the following merges: commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 Merge: 87f69f467a83 63618e71e89b Author: Tom Rini <trini@konsulko.com> Date: Fri Jan 3 09:48:47 2020 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support commit 87f69f467a8335b171c71bf217d2625d515acd7c Merge: c0912f9bbfb2 4466b9970319 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 24 08:18:19 2019 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next - Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards commit c0912f9bbfb26dd03d189953678691b799d35b6e Merge: 533c9f5714bd a1d6dc3f8407 Author: Tom Rini <trini@konsulko.com> Date: Wed Dec 18 07:20:19 2019 -0500 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1 Merge: 553cb0688782 033e18b47bd0 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 17 07:53:08 2019 -0500 Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next i2c: for next - misc: i2c_eeprom: Add partition support and add ability to query size of eeprom device and partitions - i2c common: add support for offset overflow in to address and add sandbox tests for it. commit 553cb06887825314e74a9bdac337467c77d1db88 Merge: f39abbbc531e b4f98b3b16ec Author: Tom Rini <trini@konsulko.com> Date: Thu Dec 12 08:18:59 2019 -0500 Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
2020-01-04Revert "mmc: davinci: drop struct davinci_mmc_plat"Tom Rini
Adam Ford reports that this change breaks booting on da850-evm and Bartosz Golaszewski agrees that with the impending release we should revert the change for now. With that noted: This reverts commit 21a4d80a710c79053ac1deaa65ff9b69e6c031d4. Cc: Bartosz Golaszewski <brgl@bgdev.pl> Tested-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-02video: add wrappers for ttf type files to .gitignoreDario Binacchi
The scripts/Makefile.lib generates an assembler file (*.S) to wrap the font data for each file of type ttf defined in Kconfig. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-01-02video: Avoid using #ifdef in video-uclass.cSimon Glass
This code does not really need to use #ifdef. We can use if() instead and gain build coverage without impacting code size. Change the #ifdefs to use IS_ENABLED(), etc., instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02video: Avoid using #ifdef in vidconsole-uclass.cSimon Glass
This code does not really need to use #ifdef. We can use if() instead and gain build coverage without impacting code size. Change the #ifdefs to use CONFIG_IS_ENABLED() instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02video: Avoid using #ifdef in console_rotate.cSimon Glass
This code does not really need to use #ifdef. We can use if() instead and gain build coverage without impacting code size. Change the #ifdefs to use IS_ENABLED() instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02video: Avoid using #ifdef in video blitting codeSimon Glass
This code does not really need to use #ifdef. We can use if() instead and gain build coverage without impacting code size. Change the #ifdefs to use IS_ENABLED() instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02video: x86: Enable 32-bit graphics by defaultSimon Glass
Most x86 boards that use video make use of 32bpp graphics. Enable this by default. This fixes missing graphics output on some x86 boards. Also remove the unnecessary 'default n' while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-02pci: layerscape: Manage PCIe EP compatible string via KconfigPankaj Bansal
The ep node device tree name is governed by these bindings: https://github.com/torvalds/linux/blob/master/Documentation/ devicetree/bindings/pci/layerscape-pci.txt#L24 As per above the ep compatible node contains platform name. Therefore, define the ep node compatible as CONFIG to find the pcie ep node in device tree during device tree fixup. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-01-02pci: layerscape: move PCIE related CONFIG to PCI KconfigPankaj Bansal
move the PCIE related config from arch Kconfig to PCI Kconfig. As the PCI_LAYERSCAPE driver is being used in platform other than fsl-layerscape platforms like ls102xa. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-12-28Merge tag 'u-boot-imx-20191228' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.01 ----------------- - Fixes for Nitrogen6x - Fix corruption for mx51evk - colibri i.MX6: fix broken ESDHC conversion - mx6sxsabresd: fix broken mmcdev - imx6q_logic: cleanup boot sequence - update ATF for imx8mq_evk - pfuze: fix pmic_get() Travis CI: https://travis-ci.org/sbabic/u-boot-imx/builds/630007464
2019-12-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- rk spi transfer limit fix - Gigadevice, gd25q128 support - spi-nor-core warnings
2019-12-27rtc: rx8010js: add compatible stringRobert Beckett
Add compatible string used by Linux. Allows for simpler syncing of device trees. Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27rtc: s35392a: add compatible stringsRobert Beckett
Add compatible strings used by Linux. Allows for simpler syncing of device trees. Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27rtc: rx8010sj: fix DM initializationRobert Beckett
pass the udevice by reference instead of double ref Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
2019-12-27spi: rk: Limit transfers to (64K - 1) bytesJagan Teki
The Rockchip SPI controller's length register only supports 16-bits, yielding a maximum length of 64KiB (the CTRLR1 register holds "length - 1"). Trying to transfer more than that (e.g., with a large SPI flash read) will cause the driver to hang. Now, it seems that while theoretically we should be able to program CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to cause the core to choke, so stick with a maximum of 64K - 1 bytes -- i.e., 0xffff. Note, that the size is further divided into 'minus 1' while writing into CTRLR1. This change fixed two different read issues, 1. sf read failure when with > 0x10000 2. Boot from SPI flash failed during spi_flash_read call in common/spl/spl_spi.c Observed and Tested in - Rockpro64 with Gigadevice flash - ROC-RK3399-PC with Winbond flash Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27mtd: spi-nor-core: Fix static checker warningsVignesh Raghavendra
Static checker warns 'ret' variable may be used uninitialized in spi_nor_erase() and spi_nor_write() in case of zero length requests. Fix these warnings by checking for zero length requests and returning early. Reported-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-12-27imx8m: ddr_init: Move ddr_init() messages to debug levelFabio Estevam
Currently inside ddr_init() there is a mix of printf() and debug() level messages. Since this type of information is useful for debug purposes, convert all of them to debug level for consistency. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-12-26phy: ti-pipe3: Fix SATA & USB PHY power up sequenceRoger Quadros
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-14 08:05:16 +0000