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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/atmel,hlcdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel's HLCD Controller
maintainers:
- Nicolas Ferre <nicolas.ferre@microchip.com>
- Alexandre Belloni <alexandre.belloni@bootlin.com>
- Claudiu Beznea <claudiu.beznea@tuxon.dev>
description:
The Atmel HLCDC (HLCD Controller) IP available on Atmel SoCs exposes two
subdevices, a PWM chip and a Display Controller.
properties:
compatible:
enum:
- atmel,at91sam9n12-hlcdc
- atmel,at91sam9x5-hlcdc
- atmel,sama5d2-hlcdc
- atmel,sama5d3-hlcdc
- atmel,sama5d4-hlcdc
- microchip,sam9x60-hlcdc
- microchip,sam9x75-xlcdc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 3
clock-names:
items:
- const: periph_clk
- const: sys_clk
- const: slow_clk
- const: lvds_pll_clk
minItems: 3
display-controller:
$ref: /schemas/display/atmel/atmel,hlcdc-display-controller.yaml
pwm:
$ref: /schemas/pwm/atmel,hlcdc-pwm.yaml
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
lcd_controller: lcd-controller@f0030000 {
compatible = "atmel,sama5d3-hlcdc";
reg = <0xf0030000 0x2000>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk", "sys_clk", "slow_clk";
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
display-controller {
compatible = "atmel,hlcdc-display-controller";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
hlcdc_panel_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
};
pwm {
compatible = "atmel,hlcdc-pwm";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_pwm>;
#pwm-cells = <3>;
};
};
|
