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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/mtk,scp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek SCP
maintainers:
- Tinghan Shen <tinghan.shen@mediatek.com>
description:
This binding provides support for ARM Cortex M4 Co-processor found on some
Mediatek SoCs.
properties:
compatible:
enum:
- mediatek,mt8183-scp
- mediatek,mt8186-scp
- mediatek,mt8188-scp
- mediatek,mt8192-scp
- mediatek,mt8195-scp
- mediatek,mt8195-scp-dual
reg:
description:
Should contain the address ranges for memory regions SRAM, CFG, and,
on some platforms, L1TCM.
minItems: 2
maxItems: 3
reg-names:
minItems: 2
maxItems: 3
clocks:
description:
Clock for co-processor (see ../clock/clock-bindings.txt).
Required by mt8183 and mt8192.
maxItems: 1
clock-names:
const: main
interrupts:
maxItems: 1
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description:
If present, name (or relative path) of the file within the
firmware search path containing the firmware image used when
initializing SCP.
memory-region:
maxItems: 1
cros-ec-rpmsg:
$ref: /schemas/mfd/google,cros-ec.yaml
description:
This subnode represents the rpmsg device. The properties
of this node are defined by the individual bindings for
the rpmsg devices.
required:
- mediatek,rpmsg-name
unevaluatedProperties: false
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges:
description:
Standard ranges definition providing address translations for
local SCP SRAM address spaces to bus addresses.
patternProperties:
"^scp@[a-f0-9]+$":
type: object
description:
The MediaTek SCP integrated to SoC might be a multi-core version.
The other cores are represented as child nodes of the boot core.
There are some integration differences for the IP like the usage of
address translator for translating SoC bus addresses into address space
for the processor.
Each SCP core has own cache memory. The SRAM and L1TCM are shared by
cores. The power of cache, SRAM and L1TCM power should be enabled
before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
on differnt SoCs.
The SCP cores do not use an MMU, but has a set of registers to
control the translations between 32-bit CPU addresses into system bus
addresses. Cache and memory access settings are provided through a
Memory Protection Unit (MPU), programmable only from the SCP.
properties:
compatible:
enum:
- mediatek,scp-core
reg:
description: The base address and size of SRAM.
maxItems: 1
reg-names:
const: sram
interrupts:
maxItems: 1
firmware-name:
$ref: /schemas/types.yaml#/definitions/string
description:
If present, name (or relative path) of the file within the
firmware search path containing the firmware image used when
initializing sub cores of multi-core SCP.
memory-region:
maxItems: 1
cros-ec-rpmsg:
$ref: /schemas/mfd/google,cros-ec.yaml
description:
This subnode represents the rpmsg device. The properties
of this node are defined by the individual bindings for
the rpmsg devices.
required:
- mediatek,rpmsg-name
unevaluatedProperties: false
required:
- compatible
- reg
- reg-names
additionalProperties: false
required:
- compatible
- reg
- reg-names
allOf:
- if:
properties:
compatible:
enum:
- mediatek,mt8183-scp
- mediatek,mt8192-scp
then:
required:
- clocks
- clock-names
- if:
properties:
compatible:
enum:
- mediatek,mt8183-scp
- mediatek,mt8186-scp
- mediatek,mt8188-scp
then:
properties:
reg:
maxItems: 2
reg-names:
items:
- const: sram
- const: cfg
- if:
properties:
compatible:
enum:
- mediatek,mt8192-scp
- mediatek,mt8195-scp
then:
properties:
reg:
maxItems: 3
reg-names:
items:
- const: sram
- const: cfg
- const: l1tcm
- if:
properties:
compatible:
enum:
- mediatek,mt8195-scp-dual
then:
properties:
reg:
maxItems: 2
reg-names:
items:
- const: cfg
- const: l1tcm
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8192-clk.h>
scp@10500000 {
compatible = "mediatek,mt8192-scp";
reg = <0x10500000 0x80000>,
<0x10700000 0x8000>,
<0x10720000 0xe0000>;
reg-names = "sram", "cfg", "l1tcm";
clocks = <&infracfg CLK_INFRA_SCPSYS>;
clock-names = "main";
cros-ec-rpmsg {
compatible = "google,cros-ec-rpmsg";
mediatek,rpmsg-name = "cros-ec-rpmsg";
};
};
- |
scp@10500000 {
compatible = "mediatek,mt8195-scp-dual";
reg = <0x10720000 0xe0000>,
<0x10700000 0x8000>;
reg-names = "cfg", "l1tcm";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10500000 0x100000>;
scp@0 {
compatible = "mediatek,scp-core";
reg = <0x0 0xa0000>;
reg-names = "sram";
cros-ec-rpmsg {
compatible = "google,cros-ec-rpmsg";
mediatek,rpmsg-name = "cros-ec-rpmsg";
};
};
scp@a0000 {
compatible = "mediatek,scp-core";
reg = <0xa0000 0x20000>;
reg-names = "sram";
cros-ec-rpmsg {
compatible = "google,cros-ec-rpmsg";
mediatek,rpmsg-name = "cros-ec-rpmsg";
};
};
};
|
