blob: dfc03810ca0d75e46f9ca0849a25a61183cc3503 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Synopsys, Inc. All rights reserved.
*/
/ {
aliases {
spi0 = &spi0;
};
axs10x_mb@e0000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0xe0000000 0x10000000>;
u-boot,dm-pre-reloc;
clocks {
compatible = "simple-bus";
u-boot,dm-pre-reloc;
apbclk: apbclk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
uartclk: uartclk {
compatible = "fixed-clock";
clock-frequency = <33333333>;
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
};
ethernet@18000 {
compatible = "altr,socfpga-stmmac";
reg = < 0x18000 0x2000 >;
phy-mode = "gmii";
snps,pbl = < 32 >;
clocks = <&apbclk>;
clock-names = "stmmaceth";
max-speed = <100>;
};
ehci@0x40000 {
compatible = "generic-ehci";
reg = < 0x40000 0x100 >;
};
ohci@0x60000 {
compatible = "generic-ohci";
reg = < 0x60000 0x100 >;
};
uart0: serial0@22000 {
compatible = "snps,dw-apb-uart";
reg = <0x22000 0x100>;
clocks = <&uartclk>;
reg-shift = <2>;
reg-io-width = <4>;
};
spi0: spi@0 {
compatible = "snps,dw-apb-ssi";
reg = <0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <4000000>;
clocks = <&apbclk>;
clock-names = "spi_clk";
cs-gpio = <&cs_gpio 0>;
spi_flash@0 {
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <4000000>;
};
};
cs_gpio: gpio@11218 {
compatible = "snps,creg-gpio";
reg = <0x11218 0x4>;
gpio-controller;
#gpio-cells = <1>;
gpio-bank-name = "axs-spi-cs";
gpio-count = <1>;
gpio-first-shift = <0>;
gpio-bit-per-line = <2>;
gpio-activate-val = <1>;
gpio-deactivate-val = <3>;
gpio-default-val = <1>;
};
};
};
|
