1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
/*
* Copyright (C) 2014 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Robert Baldyga <r.baldyga@samsung.com>
*
* based on arch/arm/cpu/armv7/omap3/cache.S
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
dcache_enable();
}
void disable_caches(void)
{
dcache_disable();
}
#endif
#ifndef CONFIG_SYS_L2CACHE_OFF
void v7_outer_cache_enable(void)
{
__asm(
"push {r0, r1, r2, lr}\n\t"
"mrc 15, 0, r3, cr1, cr0, 1\n\t"
"orr r3, r3, #2\n\t"
"mcr 15, 0, r3, cr1, cr0, 1\n\t"
"pop {r1, r2, r3, pc}"
);
}
void v7_outer_cache_disable(void)
{
__asm(
"push {r0, r1, r2, lr}\n\t"
"mrc 15, 0, r3, cr1, cr0, 1\n\t"
"bic r3, r3, #2\n\t"
"mcr 15, 0, r3, cr1, cr0, 1\n\t"
"pop {r1, r2, r3, pc}"
);
}
#endif
|
