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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Marvell International Ltd.
*/
#include "cn9130.dtsi" /* include SoC device tree */
/ {
model = "CN9130-CRB";
compatible = "marvell,cn9130-crb",
"marvell,cn9130",
"marvell,armada-ap806-quad",
"marvell,armada-ap806";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
i2c0 = &cp0_i2c0;
spi0 = &cp0_spi1;
gpio0 = &ap_gpio0;
gpio1 = &cp0_gpio0;
gpio2 = &cp0_gpio1;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
cp0 {
config-space {
sdhci@780000 {
vqmmc-supply = <&cp0_reg_sd_vccq>;
vmmc-supply = <&cp0_reg_sd_vcc>;
};
cp0_reg_sd_vccq: cp0_sd_vccq@0 {
compatible = "regulator-gpio";
regulator-name = "cp0_sd_vccq";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&cp0_gpio1 18 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1
3300000 0x0>;
};
cp0_reg_sd_vcc: cp0_sd_vcc@0 {
compatible = "regulator-fixed";
regulator-name = "cp0_sd_vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&cp0_gpio1 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
};
};
};
&uart0 {
status = "okay";
};
/*
* AP related configuration
*/
&ap_pinctl {
/* MPP Bus:
* SDIO [0-10, 12]
* UART0 [11,19]
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 1 1 1 1 1 1 1 1 1 1
1 3 1 0 0 0 0 0 0 3 >;
};
/* on-board eMMC - U6 */
&ap_sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&ap_emmc_pins>;
bus-width = <8>;
status = "okay";
};
/*
* CP related configuration
*/
&cp0_pinctl {
/* MPP Bus:
* [0-11] RGMII1
* [12] GPIO
* [13-16] SPI1
* [17-32] GPIO
* [33] SD_PWR_OFF
* [34] CP_PCIE0_CLKREQn
* [35-38] I2C1 I2C0
* [39] GPIO
* [40-43] SMI/XSMI
* [44-46] GPIO
* [47] UART1_TX
* [48] GPIO
* [49] SD_HST_18_EN
* [50] GPIO
* [51] SD_PWR_0
* [52] PCIE_RSTn
* [53] UART1_RX
* [54] GPIO
* [55] SD_DT
* [56-61] SDIO
*
* Note that CRB board revisions have different MPP configurations.
* r1p2 has SPI flash on MPP[30:27] and r1p3.1, which is the latest
* board revision, has it mapped to MPP[16:13].
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 3 3 3 3 3 3 3 3 3 3
3 3 0 3 3 3 3 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 6 9 2 2 2 2 0
8 8 8 8 0 0 0 7 0 0xa
0 0xa 9 7 0 0xb 0xe 0xe 0xe 0xe
0xe 0xe 0xe>;
cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
marvell,pins = < 55 >;
marvell,function = <0>;
};
cp0_spi1_pins_crb: cp0-spi-pins-crb {
marvell,pins = < 13 14 15 16 >;
marvell,function = <3>;
};
cp0_smi_pins_crb: cp0-smi-pins-crb {
marvell,pins = < 40 41 >;
marvell,function = <8>;
};
cp0_xsmi_pins_crb: cp0-xsmi-pins-crb {
marvell,pins = < 42 43 >;
marvell,function = <8>;
};
};
/*
* CP0
*/
&cp0_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
&cp0_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
};
&cp0_sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_sdhci_pins
&cp0_sdhci_cd_pins_crb>;
bus-width = <4>;
vqmmc-supply = <&cp0_reg_sd_vccq>;
vmmc-supply = <&cp0_reg_sd_vcc>;
status = "okay";
};
&cp0_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi1_pins_crb>;
reg = <0x700680 0x50>, /* control */
<0x2000000 0x1000000>, /* CS0 */
<0 0xffffffff>, /* CS1 */
<0 0xffffffff>, /* CS2 */
<0 0xffffffff>; /* CS3 */
status = "okay";
spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor", "spi-flash";
reg = <0x0>;
/* On-board MUX does not allow higher frequencies */
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x200000>;
};
partition@400000 {
label = "Filesystem";
reg = <0x200000 0xe00000>;
};
};
};
};
&cp0_utmi0 {
status = "okay";
};
&cp0_utmi1 {
status = "okay";
};
&cp0_mdio {
pinctrl-names = "default";
pinctrl-0 = <&cp0_smi_pins_crb>;
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
switch6: ethernet-switch@6 {
reg = <6>;
};
};
&cp0_xmdio {
pinctrl-names = "default";
pinctrl-0 = <&cp0_xsmi_pins_crb>;
status = "okay";
nbaset_phy0: ethernet-phy@0 {
reg = <0>;
};
};
&cp0_ethernet {
status = "okay";
};
&cp0_eth0 {
status = "okay";
phy-mode = "sfi";
};
&cp0_eth1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_ge1_rgmii_pins>;
phy = <&phy0>;
phy-mode = "rgmii-id";
};
&cp0_eth2 {
/* Disable it for now, as mainline does not support this IF yet */
status = "disabled";
phy = <&nbaset_phy0>;
};
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