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|
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright (C) 2016, Freescale Semiconductor
* Copyright 2021 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
#include "skeleton64.dtsi"
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "fsl,ls1046a";
interrupt-parent = <&gic>;
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "sysclk";
};
gic: interrupt-controller@1400000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x1410000 0 0x10000>, /* GICD */
<0x0 0x1420000 0 0x10000>, /* GICC */
<0x0 0x1440000 0 0x20000>, /* GICH */
<0x0 0x1460000 0 0x20000>; /* GICV */
interrupts = <1 9 0xf08>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
sfp: efuse@1e80000 {
compatible = "fsl,ls1021a-sfp";
reg = <0x0 0x1e80000 0x0 0x1000>;
clocks = <&clockgen 4 3>;
clock-names = "sfp";
};
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1046a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
#clock-cells = <2>;
clocks = <&sysclk>;
};
dspi0: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 64 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
dspi1: dspi@2110000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <0 65 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
esdhc: esdhc@1560000 {
compatible = "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
interrupts = <0 62 0x4>;
big-endian;
bus-width = <4>;
};
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <0 66 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2310000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <0 67 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2320000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 68 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@2330000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <0 134 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
interrupts = <0 43 0x4>;
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
"fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <0 75 0x4>;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <0 71 0x4>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <0 72 0x4>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <0 73 0x4>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <0 74 0x4>;
};
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <0 56 0x4>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c1: i2c@2190000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <0 57 0x4>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c2: i2c@21a0000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21a0000 0x0 0x10000>;
interrupts = <0 58 0x4>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c3: i2c@21b0000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21b0000 0x0 0x10000>;
interrupts = <0 59 0x4>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
duart2: serial@21d0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0500 0x0 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
duart3: serial@21d0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0600 0x0 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
interrupts = <0 48 0x4>;
clocks = <&clockgen 4 0>;
clock-names = "ipg";
status = "disabled";
};
lpuart1: serial@2960000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2960000 0x0 0x1000>;
interrupts = <0 49 0x4>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart2: serial@2970000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2970000 0x0 0x1000>;
interrupts = <0 50 0x4>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart3: serial@2980000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2980000 0x0 0x1000>;
interrupts = <0 51 0x4>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart4: serial@2990000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2990000 0x0 0x1000>;
interrupts = <0 52 0x4>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
lpuart5: serial@29a0000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x29a0000 0x0 0x1000>;
interrupts = <0 53 0x4>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
qspi: quadspi@1550000 {
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x10000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
status = "disabled";
};
usb0: usb@2f00000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
interrupts = <0 60 4>;
dr_mode = "host";
};
usb1: usb@3000000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3000000 0x0 0x10000>;
interrupts = <0 61 4>;
dr_mode = "host";
};
usb2: usb@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <0 63 4>;
dr_mode = "host";
};
pcie1: pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
0x00 0x03480000 0x0 0x40000 /* lut registers */
0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
0x40 0x00000000 0x0 0x20000>; /* configuration space */
reg-names = "dbi", "lut", "ctrl", "config";
big-endian;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
pcie_ep1: pcie_ep@3400000 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x03400000 0x0 0x80000
0x00 0x034c0000 0x0 0x40000
0x40 0x00000000 0x8 0x00000000>;
reg-names = "regs", "ctrl", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
big-endian;
};
pcie2: pcie@3500000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
0x00 0x03580000 0x0 0x40000 /* lut registers */
0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
0x48 0x00000000 0x0 0x20000>; /* configuration space */
reg-names = "dbi", "lut", "ctrl", "config";
big-endian;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <2>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
pcie_ep2: pcie_ep@3500000 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x03500000 0x0 0x80000
0x00 0x035c0000 0x0 0x40000
0x48 0x00000000 0x8 0x00000000>;
reg-names = "regs", "ctrl", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
big-endian;
};
pcie3: pcie@3600000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
0x00 0x03680000 0x0 0x40000 /* lut registers */
0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
0x50 0x00000000 0x0 0x20000>; /* configuration space */
reg-names = "dbi", "lut", "ctrl", "config";
big-endian;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
pcie_ep3: pcie_ep@3600000 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x03600000 0x0 0x80000
0x00 0x036c0000 0x0 0x40000
0x50 0x00000000 0x8 0x00000000>;
reg-names = "regs", "ctrl", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
big-endian;
};
sata: sata@3200000 {
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
reg-names = "ahci", "sata-ecc";
interrupts = <0 69 4>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
};
};
|
