1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2019
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
*/
#include <dt-bindings/memory/imxrt-sdram.h>
#include "imxrt1050-pinfunc.h"
/ {
aliases {
display0 = &lcdif;
usbphy0 = &usbphy1;
};
chosen {
bootph-pre-ram;
tick-timer = &gpt;
};
clocks {
bootph-pre-ram;
};
soc {
bootph-pre-ram;
usbphy1: usbphy@400d9000 {
compatible = "fsl,imxrt-usbphy";
reg = <0x400d9000 0x1000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
};
usbmisc: usbmisc@402e0800 {
#index-cells = <1>;
compatible = "fsl,imxrt-usbmisc";
reg = <0x402e0800 0x200>;
clocks = <&clks IMXRT1050_CLK_USBOH3>;
};
usbotg1: usb@402e0000 {
compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
reg = <0x402e0000 0x200>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1050_CLK_USBOH3>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x10>;
rx-burst-size-dword = <0x10>;
status = "disabled";
};
lcdif: lcdif@402b8000 {
compatible = "fsl,imxrt-lcdif";
reg = <0x402b8000 0x4000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
<&clks IMXRT1050_CLK_LCDIF_APB>;
clock-names = "pix", "axi";
assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
status = "disabled";
};
semc: semc@402f0000 {
compatible = "fsl,imxrt-semc";
reg = <0x402f0000 0x4000>;
clocks = <&clks IMXRT1050_CLK_SEMC>;
pinctrl-0 = <&pinctrl_semc>;
pinctrl-names = "default";
status = "okay";
};
};
};
&semc {
bootph-pre-ram;
/*
* Memory configuration from sdram datasheet IS42S16160J-6BLI
*/
fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
MUX_CSX0_SDRAM_CS1
0
0
0
0>;
fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
BL_8
COL_9BITS
CL_3>;
fsl,sdram-timing = /bits/ 8 <0x2
0x2
0x9
0x1
0x5
0x6
0x20
0x09
0x01
0x00
0x04
0x0A
0x21
0x50>;
bank1: bank@0 {
fsl,base-address = <0x80000000>;
fsl,memory-size = <MEM_SIZE_32M>;
bootph-pre-ram;
};
};
&osc {
bootph-pre-ram;
};
&anatop {
bootph-pre-ram;
};
&clks {
bootph-pre-ram;
};
&gpio1 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
bootph-pre-ram;
};
&gpio2 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
bootph-pre-ram;
};
&gpio3 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
bootph-pre-ram;
};
&gpio4 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
bootph-pre-ram;
};
&gpio5 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
bootph-pre-ram;
};
&gpt {
clocks = <&osc>;
compatible = "fsl,imxrt-gpt";
status = "okay";
bootph-pre-ram;
};
&lpuart1 { /* console */
compatible = "fsl,imxrt-lpuart";
clock-names = "per";
bootph-pre-ram;
};
&iomuxc {
bootph-pre-ram;
compatible = "fsl,imxrt-iomuxc";
pinctrl-0 = <&pinctrl_lpuart1>;
pinctrl_semc: semcgrp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
0xf1 /* SEMC_D0 */
MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
0xf1 /* SEMC_D1 */
MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
0xf1 /* SEMC_D2 */
MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
0xf1 /* SEMC_D3 */
MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
0xf1 /* SEMC_D4 */
MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
0xf1 /* SEMC_D5 */
MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
0xf1 /* SEMC_D6 */
MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
0xf1 /* SEMC_D7 */
MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
0xf1 /* SEMC_DM0 */
MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
0xf1 /* SEMC_A0 */
MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
0xf1 /* SEMC_A1 */
MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
0xf1 /* SEMC_A2 */
MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
0xf1 /* SEMC_A3 */
MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
0xf1 /* SEMC_A4 */
MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
0xf1 /* SEMC_A5 */
MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
0xf1 /* SEMC_A6 */
MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
0xf1 /* SEMC_A7 */
MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
0xf1 /* SEMC_A8 */
MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
0xf1 /* SEMC_A9 */
MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
0xf1 /* SEMC_A11 */
MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
0xf1 /* SEMC_A12 */
MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
0xf1 /* SEMC_BA0 */
MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
0xf1 /* SEMC_BA1 */
MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
0xf1 /* SEMC_A10 */
MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
0xf1 /* SEMC_CAS */
MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
0xf1 /* SEMC_RAS */
MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
0xf1 /* SEMC_CLK */
MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
0xf1 /* SEMC_CKE */
MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
0xf1 /* SEMC_WE */
MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
0xf1 /* SEMC_CS0 */
MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
0xf1 /* SEMC_D8 */
MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
0xf1 /* SEMC_D9 */
MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
0xf1 /* SEMC_D10 */
MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
0xf1 /* SEMC_D11 */
MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
0xf1 /* SEMC_D12 */
MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
0xf1 /* SEMC_D13 */
MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
0xf1 /* SEMC_D14 */
MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
0xf1 /* SEMC_D15 */
MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
0xf1 /* SEMC_DM1 */
MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
(IMX_PAD_SION | 0xf1) /* SEMC_DQS */
>;
bootph-pre-ram;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x1b0b1
MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x1b0b1
MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x0b069
MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0b069
>;
};
pinctrl_lpuart1: lpuart1grp {
bootph-pre-ram;
};
pinctrl_usdhc0: usdhc0grp {
bootph-pre-ram;
};
};
&usdhc1 {
compatible = "fsl,imxrt-usdhc";
bootph-pre-ram;
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <16>;
display-timings {
timing0: timing0 {
clock-frequency = <9300000>;
hactive = <480>;
vactive = <272>;
hback-porch = <4>;
hfront-porch = <8>;
vback-porch = <4>;
vfront-porch = <8>;
hsync-len = <41>;
vsync-len = <10>;
de-active = <1>;
pixelclk-active = <0>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};
&usbotg1 {
dr_mode = "host";
status = "okay";
};
|
