1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
|
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include "skeleton.dtsi"
/ {
compatible = "rockchip,rk3036";
interrupt-parent = <&gic>;
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
i2c1 = &i2c1;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
mmc0 = &emmc;
mmc1 = &sdmmc;
};
memory {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "rockchip,rk3036-smp";
cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
operating-points = <
/* KHz uV */
816000 1000000
>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
resets = <&cru SRST_CORE0>;
};
cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
};
};
amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pdma: pdma@20078000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20078000 0x4000>;
arm,pl330-broken-no-flushp;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC2>;
clock-names = "apb_pclk";
};
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};
cru: clock-controller@20000000 {
compatible = "rockchip,rk3036-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>;
assigned-clock-rates = <594000000>;
};
uart0: serial@20060000 {
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
reg = <0x20060000 0x100>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
};
uart1: serial@20064000 {
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
reg = <0x20064000 0x100>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
};
uart2: serial@20068000 {
compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
reg = <0x20068000 0x100>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
};
pwm0: pwm@20050000 {
compatible = "rockchip,rk2928-pwm";
reg = <0x20050000 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
status = "disabled";
};
pwm1: pwm@20050010 {
compatible = "rockchip,rk2928-pwm";
reg = <0x20050010 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
status = "disabled";
};
pwm2: pwm@20050020 {
compatible = "rockchip,rk2928-pwm";
reg = <0x20050020 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
status = "disabled";
};
pwm3: pwm@20050030 {
compatible = "rockchip,rk2928-pwm";
reg = <0x20050030 0x10>;
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
status = "disabled";
};
sram: sram@10080000 {
compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
reg = <0x10080000 0x2000>;
};
gic: interrupt-controller@10139000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x10139000 0x1000>,
<0x1013a000 0x1000>,
<0x1013c000 0x2000>,
<0x1013e000 0x2000>;
interrupts = <GIC_PPI 9 0xf04>;
};
grf: syscon@20008000 {
compatible = "rockchip,rk3036-grf", "syscon";
reg = <0x20008000 0x1000>;
};
usb_otg: usb@10180000 {
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x10180000 0x40000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG0>;
clock-names = "otg";
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <275>;
g-tx-fifo-size = <256 128 128 64 64 32>;
g-use-dma;
status = "disabled";
};
usb_host: usb@101c0000 {
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
"snps,dwc2";
reg = <0x101c0000 0x40000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG1>;
clock-names = "otg";
dr_mode = "host";
status = "disabled";
};
emmc: dwmmc@1021c000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-frequency = <37500000>;
max-frequency = <37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
dmas = <&pdma 12>;
dma-names = "rx-tx";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x1021c000 0x4000>;
broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
disable-wp;
fifo-mode;
non-removable;
num-slots = <1>;
default-sample-phase = <158>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
};
sdmmc: dwmmc@10214000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
clock-frequency = <37500000>;
max-frequency = <37500000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3036-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio0@2007c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2007c000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio2@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
emmc {
/*
* We run eMMC at max speed; bump up drive strength.
* We also have external pulls, so disable the internal ones.
*/
emmc_clk: emmc-clk {
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
<1 25 RK_FUNC_2 &pcfg_pull_none>,
<1 26 RK_FUNC_2 &pcfg_pull_none>,
<1 27 RK_FUNC_2 &pcfg_pull_none>;
/*
<1 28 RK_FUNC_2 &pcfg_pull_up>,
<1 29 RK_FUNC_2 &pcfg_pull_up>,
<1 30 RK_FUNC_2 &pcfg_pull_up>,
<1 31 RK_FUNC_2 &pcfg_pull_up>;
*/
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
<0 17 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
<2 23 RK_FUNC_1 &pcfg_pull_none>;
};
/* no rts / cts for uart1 */
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
<1 19 RK_FUNC_2 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <0 1 2 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <0 27 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
<0 3 RK_FUNC_1 &pcfg_pull_none>;
};
};
};
i2c1: i2c@20056000 {
compatible = "rockchip,rk3288-i2c";
reg = <0x20056000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
status = "disabled";
};
};
|
