blob: d24f621cd66952063c1fc7b1b9c09087bb09fd2a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
|
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
* Copyright (c) 2018 Simon Goldschmidt
*/
#include "socfpga-common-u-boot.dtsi"
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb1;
};
};
&can0 {
status = "okay";
};
&watchdog0 {
status = "disabled";
};
&mmc {
u-boot,dm-pre-reloc;
};
&qspi {
u-boot,dm-pre-reloc;
};
&flash0 {
compatible = "n25q00", "jedec,spi-nor";
u-boot,dm-pre-reloc;
partition@qspi-boot {
/* 8MB for raw data. */
label = "Flash 0 Raw Data";
reg = <0x0 0x800000>;
};
partition@qspi-rootfs {
/* 120MB for jffs2 data. */
label = "Flash 0 jffs2 Filesystem";
reg = <0x800000 0x7800000>;
};
};
&uart0 {
clock-frequency = <100000000>;
u-boot,dm-pre-reloc;
};
&uart1 {
clock-frequency = <100000000>;
};
&porta {
bank-name = "porta";
};
&portb {
bank-name = "portb";
};
&portc {
bank-name = "portc";
};
&i2c0 {
i2c-scl-falling-time-ns = <300>;
};
|