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// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx Versal Mini OSPI Configuration
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
*/
/dts-v1/;
/ {
compatible = "xlnx,versal";
#address-cells = <2>;
#size-cells = <2>;
model = "Xilinx Versal MINI OSPI";
clk125: clk125 {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <125000000>;
};
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
bootph-all;
};
amba: amba {
bootph-all;
compatible = "simple-bus";
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
ospi: spi@f1010000 {
compatible = "cadence,qspi", "cdns,qspi-nor";
status = "okay";
reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
clock-names = "ref_clk", "pclk";
clocks = <&clk125 &clk125>;
bus-num = <2>;
num-cs = <1>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,is-dma = <1>;
cdns,trigger-address = <0xc0000000>;
#address-cells = <1>;
#size-cells = <0>;
flash0: flash@0 {
compatible = "n25q512a", "micron,m25p80",
"jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <20000000>;
};
};
};
aliases {
serial0 = &dcc;
spi0 = &ospi;
};
chosen {
stdout-path = "serial0:115200";
};
memory@fffc0000 {
device_type = "memory";
reg = <0x0 0xfffc0000 0x0 0x40000>;
};
};
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