arch/arm/dts/zynq-zc770-xm013.dts


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92

// SPDX-License-Identifier: GPL-2.0+
/*
 * Xilinx ZC770 XM013 board DTS
 *
 * Copyright (C) 2013 Xilinx, Inc.
 */
/dts-v1/;
#include "zynq-7000.dtsi"

/ {
	model = "Xilinx ZC770 XM013 board";
	compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";

	aliases {
		ethernet0 = &gem1;
		i2c0 = &i2c1;
		serial0 = &uart0;
		spi0 = &qspi;
		spi1 = &spi0;
	};

	chosen {
		bootargs = "";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};
};

&can1 {
	status = "okay";
};

&gem1 {
	status = "okay";
	phy-mode = "rgmii-id";
	phy-handle = <&ethernet_phy>;

	ethernet_phy: ethernet-phy@7 {
		reg = <7>;
		device_type = "ethernet-phy";
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	si570: clock-generator@55 {
		#clock-cells = <0>;
		compatible = "silabs,si570";
		temperature-stability = <50>;
		reg = <0x55>;
		factory-fout = <156250000>;
		clock-frequency = <148500000>;
	};
};

&qspi {
	status = "okay";
	num-cs = <2>;
	flash@0 {
		compatible = "n25q128a11", "jedec,spi-nor";
		reg = <0>, <1>;
		parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <50000000>;
	};
};

&spi0 {
	status = "okay";
	num-cs = <4>;
	is-decoded-cs = <0>;
	eeprom: eeprom@2 {
		compatible = "atmel,at25";
		reg = <2>;
		spi-max-frequency = <1000000>;
		size = <8192>;
		address-width = <16>;
		pagesize = <32>;
	};
};

&uart0 {
	bootph-all;
	status = "okay";
};