aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/dts/mediatek,mt7621-rfb.dts
blob: ff7eaf0f20e1a4255f334bef50f4ecb5460b9584 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 MediaTek Inc. All rights reserved.
 *
 * Author: Weijie Gao <weijie.gao@mediatek.com>
 */

/dts-v1/;

#include "mt7621.dtsi"

/ {
	compatible = "mediatek,mt7621-rfb", "mediatek,mt7621-soc";
	model = "MediaTek MT7621 RFB (SPI-NOR)";

	aliases {
		serial0 = &uart0;
		spi0 = &spi;
	};

	chosen {
		stdout-path = &uart0;
	};
};

&pinctrl {
	state_default: pin_state {
		gpios {
			groups = "i2c", "uart3", "pcie reset";
			function = "gpio";
		};

		wdt {
			groups = "wdt";
			function = "wdt rst";
		};

		jtag {
			groups = "jtag";
			function = "jtag";
		};
	};
};

&uart0 {
	status = "okay";
};

&gpio {
	status = "okay";
};

&spi {
	status = "okay";
	num-cs = <2>;

	spi-flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <25000000>;
		reg = <0>;
	};
};

&eth {
	status = "okay";
};

&mmc {
	cap-sd-highspeed;

	status = "okay";
};

&ssusb {
	status = "okay";
};

&u3phy {
	status = "okay";
};