blob: 870010f0e40dc81893cb6e752827c76cea537b9e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
|
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "skeleton.dtsi"
/ {
compatible = "qca,qca953x";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "mips,mips24Kc";
reg = <0>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
xtal: xtal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-output-names = "xtal";
};
};
pinctrl {
u-boot,dm-pre-reloc;
compatible = "qca,qca953x-pinctrl";
ranges;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x18040000 0x100>;
};
ahb {
compatible = "simple-bus";
ranges;
#address-cells = <1>;
#size-cells = <1>;
apb {
compatible = "simple-bus";
ranges;
#address-cells = <1>;
#size-cells = <1>;
uart0: uart@18020000 {
compatible = "ns16550";
reg = <0x18020000 0x20>;
reg-shift = <2>;
clock-frequency = <25000000>;
interrupts = <128 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
spi0: spi@1f000000 {
compatible = "qca,ar7100-spi";
reg = <0x1f000000 0x10>;
interrupts = <129 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
};
|