1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
|
/* Only eth0 supported for now
*
* (C) Copyright 2003
* Thomas.Lange@corelatus.se
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#if defined(CONFIG_SYS_DISCOVER_PHY)
#error "PHY not supported yet"
/* We just assume that we are running 100FD for now */
/* We all use switches, right? ;-) */
#endif
/* I assume ethernet behaves like au1000 */
#ifdef CONFIG_SOC_AU1000
/* Base address differ between cpu:s */
#define ETH0_BASE AU1000_ETH0_BASE
#define MAC0_ENABLE AU1000_MAC0_ENABLE
#else
#ifdef CONFIG_SOC_AU1100
#define ETH0_BASE AU1100_ETH0_BASE
#define MAC0_ENABLE AU1100_MAC0_ENABLE
#else
#ifdef CONFIG_SOC_AU1500
#define ETH0_BASE AU1500_ETH0_BASE
#define MAC0_ENABLE AU1500_MAC0_ENABLE
#else
#ifdef CONFIG_SOC_AU1550
#define ETH0_BASE AU1550_ETH0_BASE
#define MAC0_ENABLE AU1550_MAC0_ENABLE
#else
#error "No valid cpu set"
#endif
#endif
#endif
#endif
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#include <asm/io.h>
#include <asm/au1x00.h>
#if defined(CONFIG_CMD_MII)
#include <miiphy.h>
#endif
/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520
#define PKT_MAXBUF_SIZE 1518
static char txbuf[DBUF_LENGTH];
static int next_tx;
static int next_rx;
/* 4 rx and 4 tx fifos */
#define NO_OF_FIFOS 4
typedef struct{
u32 status;
u32 addr;
u32 len; /* Only used for tx */
u32 not_used;
} mac_fifo_t;
mac_fifo_t mac_fifo[NO_OF_FIFOS];
#define MAX_WAIT 1000
#if defined(CONFIG_CMD_MII)
int au1x00_miiphy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short * value)
{
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
u32 mii_control;
unsigned int timedout = 20;
while (*mii_control_reg & MAC_MII_BUSY) {
udelay(1000);
if (--timedout == 0) {
printf("au1x00_eth: miiphy_read busy timeout!!\n");
return -1;
}
}
mii_control = MAC_SET_MII_SELECT_REG(reg) |
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
*mii_control_reg = mii_control;
timedout = 20;
while (*mii_control_reg & MAC_MII_BUSY) {
udelay(1000);
if (--timedout == 0) {
printf("au1x00_eth: miiphy_read busy timeout!!\n");
return -1;
}
}
*value = *mii_data_reg;
return 0;
}
int au1x00_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
u32 mii_control;
unsigned int timedout = 20;
while (*mii_control_reg & MAC_MII_BUSY) {
udelay(1000);
if (--timedout == 0) {
printf("au1x00_eth: miiphy_write busy timeout!!\n");
return -1;
}
}
mii_control = MAC_SET_MII_SELECT_REG(reg) |
MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
*mii_data_reg = value;
*mii_control_reg = mii_control;
return 0;
}
#endif
static int au1x00_send(struct eth_device *dev, void *packet, int length)
{
volatile mac_fifo_t *fifo_tx =
(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
int i;
int res;
/* tx fifo should always be idle */
fifo_tx[next_tx].len = length;
fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
au_sync();
udelay(1);
i=0;
while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
if(i>MAX_WAIT){
printf("TX timeout\n");
break;
}
udelay(1);
i++;
}
/* Clear done bit */
fifo_tx[next_tx].addr = 0;
fifo_tx[next_tx].len = 0;
au_sync();
res = fifo_tx[next_tx].status;
next_tx++;
if(next_tx>=NO_OF_FIFOS){
next_tx=0;
}
return(res);
}
static int au1x00_recv(struct eth_device* dev){
volatile mac_fifo_t *fifo_rx =
(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
int length;
u32 status;
for(;;){
if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
/* Nothing has been received */
return(-1);
}
status = fifo_rx[next_rx].status;
length = status&0x3FFF;
if(status&RX_ERROR){
printf("Rx error 0x%x\n", status);
} else {
/* Pass the packet up to the protocol layers. */
net_process_received_packet(net_rx_packets[next_rx],
length - 4);
}
fifo_rx[next_rx].addr =
(virt_to_phys(net_rx_packets[next_rx])) | RX_DMA_ENABLE;
next_rx++;
if(next_rx>=NO_OF_FIFOS){
next_rx=0;
}
} /* for */
return(0); /* Does anyone use this? */
}
static int au1x00_init(struct eth_device* dev, bd_t * bd){
volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
volatile mac_fifo_t *fifo_tx =
(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
volatile mac_fifo_t *fifo_rx =
(volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
int i;
next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
/* We have to enable clocks before releasing reset */
*macen = MAC_EN_CLOCK_ENABLE;
udelay(10);
/* Enable MAC0 */
/* We have to release reset before accessing registers */
*macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
MAC_EN_RESET1|MAC_EN_RESET2;
udelay(10);
for(i=0;i<NO_OF_FIFOS;i++){
fifo_tx[i].len = 0;
fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
fifo_rx[i].addr = (virt_to_phys(net_rx_packets[i])) |
RX_DMA_ENABLE;
}
/* Put mac addr in little endian */
#define ea eth_get_ethaddr()
*mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
*mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
(ea[1] << 8) | (ea[0] ) ;
#undef ea
*mac_mcast_low = 0;
*mac_mcast_high = 0;
/* Make sure the MAC buffer is in the correct endian mode */
#ifdef __LITTLE_ENDIAN
*mac_ctrl = MAC_FULL_DUPLEX;
udelay(1);
*mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
#else
*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
udelay(1);
*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
#endif
return(1);
}
static void au1x00_halt(struct eth_device* dev){
volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
/* Put MAC0 in reset */
*macen = 0;
}
int au1x00_enet_initialize(bd_t *bis){
struct eth_device* dev;
if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
puts ("malloc failed\n");
return -1;
}
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "Au1X00 ethernet");
dev->iobase = 0;
dev->priv = 0;
dev->init = au1x00_init;
dev->halt = au1x00_halt;
dev->send = au1x00_send;
dev->recv = au1x00_recv;
eth_register(dev);
#if defined(CONFIG_CMD_MII)
miiphy_register(dev->name,
au1x00_miiphy_read, au1x00_miiphy_write);
#endif
return 1;
}
int cpu_eth_init(bd_t *bis)
{
au1x00_enet_initialize(bis);
return 0;
}
|
