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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2041RDB Device Tree Source
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019-2020 NXP
*/
/include/ "p2041.dtsi"
/ {
model = "fsl,P2041RDB";
compatible = "fsl,P2041RDB";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_2 = &phy_sgmii_2;
phy_sgmii_3 = &phy_sgmii_3;
phy_sgmii_4 = &phy_sgmii_4;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_2 = &phy_xgmii_2;
spi0 = &espi0;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@e1120 {
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
phy_sgmii_2: ethernet-phy@2 {
reg = <0x2>;
};
phy_sgmii_3: ethernet-phy@3 {
reg = <0x3>;
};
phy_sgmii_4: ethernet-phy@4 {
reg = <0x4>;
};
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_3>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_4>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_2>;
phy-connection-type = "xgmii";
};
mdio@f1000 {
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
/* input clock */
spi-max-frequency = <10000000>;
};
};
/include/ "p2041si-post.dtsi"
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