blob: 4de814ea8d9ddb3f3a074c8e462905ed87c0500d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
|
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* T2080RDB Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019-2021 NXP
*/
/include/ "t2080.dtsi"
/ {
model = "fsl,T2080RDB";
compatible = "fsl,T2080RDB";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
spi0 = &espi0;
};
};
&soc {
fman@400000 {
ethernet@e0000 {
phy-handle = <&xg_aq1202_phy3>;
phy-connection-type = "xgmii";
};
ethernet@e2000 {
phy-handle = <&xg_aq1202_phy4>;
phy-connection-type = "xgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&xg_cs4315_phy2>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xg_cs4315_phy1>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
mdio@fd000 {
xg_cs4315_phy1: ethernet-phy@c {
compatible = "ethernet-phy-id13e5.1002";
reg = <0xc>;
};
xg_cs4315_phy2: ethernet-phy@d {
compatible = "ethernet-phy-id13e5.1002";
reg = <0xd>;
};
xg_aq1202_phy3: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
#ifdef CONFIG_T2080RDB_REV_D
xg_aq1202_phy4: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x8>;
};
#else
xg_aq1202_phy4: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
#endif
};
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor"; /* 16MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};
&i2c0 {
status = "okay";
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
/include/ "t2080si-post.dtsi"
|
