1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
|
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <rtc.h>
#include <asm/acpi_s3.h>
#include <asm/cmos_layout.h>
#include <asm/early_cmos.h>
#include <asm/io.h>
#include <asm/mrccache.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/fsp/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
extern void ich_spi_config_opcode(struct udevice *dev);
int checkcpu(void)
{
return 0;
}
int print_cpuinfo(void)
{
post_code(POST_CPU_INFO);
return default_print_cpuinfo();
}
int fsp_init_phase_pci(void)
{
u32 status;
/* call into FspNotify */
debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
status = fsp_notify(NULL, INIT_PHASE_PCI);
if (status)
debug("fail, error code %x\n", status);
else
debug("OK\n");
return status ? -EPERM : 0;
}
void board_final_cleanup(void)
{
u32 status;
#ifdef CONFIG_FSP_LOCKDOWN_SPI
struct udevice *dev;
/*
* Some Intel FSP (like Braswell) does SPI lock-down during the call
* to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
* it's bootloader's responsibility to configure the SPI controller's
* opcode registers properly otherwise SPI controller driver doesn't
* know how to communicate with the SPI flash device.
*
* Note we cannot do such configuration elsewhere (eg: during the SPI
* controller driver's probe() routine), because:
*
* 1). U-Boot SPI controller driver does not set the lock-down bit
* 2). Any SPI transfer will corrupt the contents of these registers
*
* Hence we have to do it right here before SPI lock-down bit is set.
*/
if (!uclass_first_device_err(UCLASS_SPI, &dev))
ich_spi_config_opcode(dev);
#endif
/* call into FspNotify */
debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
status = fsp_notify(NULL, INIT_PHASE_BOOT);
if (status)
debug("fail, error code %x\n", status);
else
debug("OK\n");
return;
}
static __maybe_unused void *fsp_prepare_mrc_cache(void)
{
struct mrc_data_container *cache;
struct mrc_region entry;
int ret;
ret = mrccache_get_region(NULL, &entry);
if (ret)
return NULL;
cache = mrccache_find_current(&entry);
if (!cache)
return NULL;
debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
cache->data, cache->data_size, cache->checksum);
return cache->data;
}
#ifdef CONFIG_HAVE_ACPI_RESUME
int fsp_save_s3_stack(void)
{
struct udevice *dev;
int ret;
if (gd->arch.prev_sleep_state == ACPI_S3)
return 0;
ret = uclass_get_device(UCLASS_RTC, 0, &dev);
if (ret) {
debug("Cannot find RTC: err=%d\n", ret);
return -ENODEV;
}
/* Save the stack address to CMOS */
ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
if (ret) {
debug("Save stack address to CMOS: err=%d\n", ret);
return -EIO;
}
return 0;
}
#endif
int arch_fsp_init(void)
{
void *nvs;
int stack = CONFIG_FSP_TEMP_RAM_ADDR;
int boot_mode = BOOT_FULL_CONFIG;
#ifdef CONFIG_HAVE_ACPI_RESUME
int prev_sleep_state = chipset_prev_sleep_state();
gd->arch.prev_sleep_state = prev_sleep_state;
#endif
if (!gd->arch.hob_list) {
#ifdef CONFIG_ENABLE_MRC_CACHE
nvs = fsp_prepare_mrc_cache();
#else
nvs = NULL;
#endif
#ifdef CONFIG_HAVE_ACPI_RESUME
if (prev_sleep_state == ACPI_S3) {
if (nvs == NULL) {
/* If waking from S3 and no cache then */
debug("No MRC cache found in S3 resume path\n");
post_code(POST_RESUME_FAILURE);
/* Clear Sleep Type */
chipset_clear_sleep_state();
/* Reboot */
debug("Rebooting..\n");
reset_cpu(0);
/* Should not reach here.. */
panic("Reboot System");
}
/*
* DM is not avaiable yet at this point, hence call
* CMOS access library which does not depend on DM.
*/
stack = cmos_read32(CMOS_FSP_STACK_ADDR);
boot_mode = BOOT_ON_S3_RESUME;
}
#endif
/*
* The first time we enter here, call fsp_init().
* Note the execution does not return to this function,
* instead it jumps to fsp_continue().
*/
fsp_init(stack, boot_mode, nvs);
} else {
/*
* The second time we enter here, adjust the size of malloc()
* pool before relocation. Given gd->malloc_base was adjusted
* after the call to board_init_f_init_reserve() in arch/x86/
* cpu/start.S, we should fix up gd->malloc_limit here.
*/
gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
}
return 0;
}
|
