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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
*/
#include <common.h>
#include <env.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <asm/arch-imx9/ccm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-imx9/imx93_pins.h>
#include <asm/arch/clock.h>
#include <power/pmic.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <usb.h>
#include <dwc3-uboot.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_FSEL2)
#define WDOG_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(LPUART1_CLK_ROOT);
return 0;
}
static int setup_fec(void)
{
return set_clk_enet(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
static int setup_eqos(void)
{
struct blk_ctrl_wakeupmix_regs *bctrl =
(struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&bctrl->eqos_gpr,
BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
return set_clk_eqos(ENET_125MHZ);
}
int board_init(void)
{
if (CONFIG_IS_ENABLED(FEC_MXC))
setup_fec();
if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
setup_eqos();
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_env_init();
#endif
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "11X11_EVK");
env_set("board_rev", "iMX93");
#endif
return 0;
}
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