blob: 23080c1798b78f7bd5901e026cdfb5130e52165d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 Google
*/
#include <common.h>
#include <dm.h>
#include <init.h>
#ifdef CONFIG_SPL_BUILD
/* provided to defeat compiler optimisation in board_init_f() */
void gru_dummy_function(int i)
{
}
int board_early_init_f(void)
{
# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
int sum, i;
/*
* Add a delay and ensure that the compiler does not optimise this out.
* This is needed since the power rails tail a while to turn on, and
* we get garbage serial output otherwise.
*/
sum = 0;
for (i = 0; i < 150000; i++)
sum += i;
gru_dummy_function(sum);
#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
return 0;
}
#endif
#ifndef CONFIG_SPL_BUILD
int board_early_init_r(void)
{
struct udevice *clk;
int ret;
/*
* This init is done in SPL, but when chain-loading U-Boot SPL will
* have been skipped. Allow the clock driver to check if it needs
* setting up.
*/
ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_DRIVER_GET(clk_rk3399), &clk);
if (ret) {
debug("%s: CLK init failed: %d\n", __func__, ret);
return ret;
}
return 0;
}
#endif
|
