1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* Copyright (C) 2007 Logic Product Development, Inc.
* Peter Barada <peterb@logicpd.com>
*
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* (C) Copyright 2008 - 2010
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*/
#include <common.h>
#include <env.h>
#include <fdt_support.h>
#include <init.h>
#include <ioports.h>
#include <log.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <pci.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <post.h>
#include "../common/common.h"
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(TARGET_KMCOGE5NE) || CONFIG_IS_ENABLED(TARGET_KMETER1)
#define CFG_SYS_DDR_MODE 0x47860452
#define CFG_SYS_DDR_INTERVAL (\
(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
#define CFG_SYS_DDR_TIMING_0 (\
(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
(0 << TIMING_CFG0_WWT_SHIFT) | \
(0 << TIMING_CFG0_RRT_SHIFT) | \
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
(3 << TIMING_CFG1_WRREC_SHIFT) | \
(7 << TIMING_CFG1_REFREC_SHIFT) | \
(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
(3 << TIMING_CFG1_PRETOACT_SHIFT))
#define CFG_SYS_DDR_TIMING_2 (\
(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
(5 << TIMING_CFG2_CPO_SHIFT) | \
(0 << TIMING_CFG2_ADD_LAT_SHIFT))
#define CFG_SYS_DDR_TIMING_3 0x00000000
#else
#define CFG_SYS_DDR_MODE 0x47860242
#define CFG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
#define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
(0 << TIMING_CFG0_WWT_SHIFT) | \
(0 << TIMING_CFG0_RRT_SHIFT) | \
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
(3 << TIMING_CFG1_WRREC_SHIFT) | \
(7 << TIMING_CFG1_REFREC_SHIFT) | \
(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
(7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
(3 << TIMING_CFG1_PRETOACT_SHIFT))
#define CFG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
(3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
(5 << TIMING_CFG2_CPO_SHIFT))
#define CFG_SYS_DDR_TIMING_3 0x00000000
#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ODT_WR_CFG | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10)
#endif
#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
SDRAM_CFG_32_BE | \
SDRAM_CFG_SREN | \
SDRAM_CFG_HSE)
#define CFG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000
#define CFG_SYS_DDR_CS0_BNDS 0x0000007f
#define CFG_SYS_DDR_MODE2 0x8080c000
#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
static int piggy_present(void)
{
struct km_bec_fpga __iomem *base =
(struct km_bec_fpga __iomem *)CFG_SYS_KMBEC_FPGA_BASE;
return in_8(&base->bprth) & PIGGY_PRESENT;
}
int ethernet_present(void)
{
return piggy_present();
}
int board_early_init_r(void)
{
struct km_bec_fpga *base =
(struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
#if defined(CONFIG_ARCH_MPC8360)
unsigned short svid;
/*
* Because of errata in the UCCs, we have to write to the reserved
* registers to slow the clocks down.
*/
svid = SVR_REV(mfspr(SVR));
switch (svid) {
case 0x0020:
/*
* MPC8360ECE.pdf QE_ENET10 table 4:
* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
*/
setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
break;
case 0x0021:
/*
* MPC8360ECE.pdf QE_ENET10 table 4:
* IMMR + 0x14AC[24:27] = 1010
*/
clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
0x00000050, 0x000000a0);
break;
}
#endif
/* enable the PHY on the PIGGY */
setbits_8(&base->pgy_eth, 0x01);
/* enable the Unit LED (green) */
setbits_8(&base->oprth, WRL_BOOT);
/* enable Application Buffer */
setbits_8(&base->oprtl, OPRTL_XBUFENA);
return 0;
}
int misc_init_r(void)
{
ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
return 0;
}
int last_stage_init(void)
{
#if defined(CONFIG_TARGET_KMCOGE5NE)
/*
* BFTIC3 on the local bus CS4
*/
struct bfticu_iomap *base = (struct bfticu_iomap *)0xB0000000;
u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
if (dip_switch != 0) {
/* start bootloader */
puts("DIP: Enabled\n");
env_set("actual_bank", "0");
}
#endif
set_km_env();
return 0;
}
static int fixed_sdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
out_be32(&im->ddr.csbnds[0].csbnds, (CFG_SYS_DDR_CS0_BNDS) | 0x7f);
out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2);
out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE);
out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2);
out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL);
out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL);
udelay(200);
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
disable_addr_trans();
msize = get_ram_size(CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
enable_addr_trans();
msize /= (1024 * 1024);
if (CFG_SYS_SDRAM_SIZE >> 20 != msize) {
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size >> 1, ddr_size_log2++)
if (ddr_size & 1)
return -1;
out_be32(&im->sysconf.ddrlaw[0].ar,
(LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
out_be32(&im->ddr.csbnds[0].csbnds,
(((msize / 16) - 1) & 0xff));
}
return msize;
}
int dram_init(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
return -ENXIO;
out_be32(&im->sysconf.ddrlaw[0].bar,
CFG_SYS_SDRAM_BASE & LAWBAR_BAR);
msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize DDR ECC byte
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
/* return total bus SDRAM size(bytes) -- DDR */
gd->ram_size = msize * 1024 * 1024;
return 0;
}
int checkboard(void)
{
puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
if (piggy_present())
puts(" with PIGGY.");
puts("\n");
return 0;
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#if defined(CONFIG_HUSH_INIT_VAR)
int hush_init_var(void)
{
ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
return 0;
}
#endif
#if defined(CONFIG_POST)
int post_hotkeys_pressed(void)
{
int testpin = 0;
struct km_bec_fpga *base =
(struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE;
int testpin_reg = in_8(&base->CFG_TESTPIN_REG);
testpin = (testpin_reg & CFG_TESTPIN_MASK) != 0;
debug("post_hotkeys_pressed: %d\n", !testpin);
return testpin;
}
ulong post_word_load(void)
{
void* addr = (ulong *) (CPM_POST_WORD_ADDR);
debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
return in_le32(addr);
}
void post_word_store(ulong value)
{
void* addr = (ulong *) (CPM_POST_WORD_ADDR);
debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
out_le32(addr, value);
}
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
*vstart = CONFIG_SYS_MEMTEST_START;
*size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
return 0;
}
#endif
|
