blob: d646df8b04cb6f5d2e26c84e6d6b34d84ad14f66 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
|
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <cpu_func.h>
#include <stdint.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_CACHELINE_SIZE
# define MEMSIZE_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
#else
/* Just use the greatest cache flush alignment requirement I'm aware of */
# define MEMSIZE_CACHELINE_SIZE 128
#endif
#ifdef __PPC__
/*
* At least on G2 PowerPC cores, sequential accesses to non-existent
* memory must be synchronized.
*/
# include <asm/io.h> /* for sync() */
#else
# define sync() /* nothing */
#endif
static void dcache_flush_invalidate(volatile long *p)
{
uintptr_t start, stop;
start = ALIGN_DOWN((uintptr_t)p, MEMSIZE_CACHELINE_SIZE);
stop = start + MEMSIZE_CACHELINE_SIZE;
flush_dcache_range(start, stop);
invalidate_dcache_range(start, stop);
}
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'.
*/
long get_ram_size(long *base, long maxsize)
{
volatile long *addr;
long save[BITS_PER_LONG - 1];
long save_base;
long cnt;
long val;
long size;
int i = 0;
int dcache_en = dcache_status();
for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
sync();
save[i++] = *addr;
sync();
*addr = ~cnt;
if (dcache_en)
dcache_flush_invalidate(addr);
}
addr = base;
sync();
save_base = *addr;
sync();
*addr = 0;
sync();
if (dcache_en)
dcache_flush_invalidate(addr);
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function. */
sync();
*base = save_base;
for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
addr = base + cnt;
sync();
*addr = save[--i];
}
return (0);
}
for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
size = cnt * sizeof(long);
/*
* Restore the original data
* before leaving the function.
*/
for (cnt <<= 1;
cnt < maxsize / sizeof(long);
cnt <<= 1) {
addr = base + cnt;
*addr = save[--i];
}
/* warning: don't restore save_base in this case,
* it is already done in the loop because
* base and base+size share the same physical memory
* and *base is saved after *(base+size) modification
* in first loop
*/
return (size);
}
}
*base = save_base;
return (maxsize);
}
phys_size_t __weak get_effective_memsize(void)
{
phys_size_t ram_size = gd->ram_size;
#ifdef CONFIG_MPC85xx
/*
* Check for overflow and limit ram size to some representable value.
* It is required that ram_base + ram_size must be representable by
* phys_size_t type and must be aligned by direct access, therefore
* calculate it from last 4kB sector which should work as alignment
* on any platform.
*/
if (gd->ram_base + ram_size < gd->ram_base)
ram_size = ((phys_size_t)~0xfffULL) - gd->ram_base;
#endif
#ifndef CFG_MAX_MEM_MAPPED
return ram_size;
#else
/* limit stack to what we can reasonable map */
return ((ram_size > CFG_MAX_MEM_MAPPED) ?
CFG_MAX_MEM_MAPPED : ram_size);
#endif
}
|
