1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
|
.. SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
.. sectionauthor:: Apurva Nandan <a-nandan@ti.com>
J784S4 and AM69 Platforms
=========================
Introduction
------------
The J784S4 SoC belongs to the K3 Multicore SoC architecture
platform, providing advanced system integration in automotive,
ADAS and industrial applications requiring AI at the network edge.
This SoC extends the K3 Jacinto 7 family of SoCs with focus on
raising performance and integration while providing interfaces,
memory architecture and compute performance for multi-sensor, high
concurrency applications.
The device is partitioned into three functional domains, each containing
specific processing cores and peripherals:
1. Wake-up (WKUP) domain
* ARM Cortex-M4F processor, runs TI Foundational Security (TIFS)
2. Microcontroller (MCU) domain
* Dual core ARM Cortex-R5F processor, runs device management
and SoC early boot
3. MAIN domain
* Two clusters of quad core 64-bit ARM Cortex-A72, runs HLOS
* Dual core ARM Cortex-R5F processor used for RTOS applications
* Four C7x DSPs used for Machine Learning applications.
More info can be found in TRM: http://www.ti.com/lit/zip/spruj52
Platform information:
* https://www.ti.com/tool/J784S4XEVM
* https://www.ti.com/tool/SK-AM69
Boot Flow
---------
Below is the pictorial representation of boot flow:
.. image:: img/boot_diagram_k3_current.svg
:alt: K3 boot flow
- On this platform, "TI Foundational Security" (TIFS) functions as the
security enclave master. While "Device Manager" (DM), also known as the
"TISCI server" in TI terminology, offers all the essential services.
- As illustrated in the diagram above, R5 SPL manages power and clock
services independently before handing over control to DM. The A72 or
the C7x (Aux core) software components request TIFS/DM to handle
security or device management services.
Sources
-------
.. include:: k3.rst
:start-after: .. k3_rst_include_start_boot_sources
:end-before: .. k3_rst_include_end_boot_sources
Build procedure
---------------
0. Setup the environment variables:
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_desc
:end-before: .. k3_rst_include_end_common_env_vars_desc
.. include:: k3.rst
:start-after: .. k3_rst_include_start_board_env_vars_desc
:end-before: .. k3_rst_include_end_board_env_vars_desc
Set the variables corresponding to this platform:
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
.. code-block:: bash
$ export UBOOT_CFG_CORTEXR=j784s4_evm_r5_defconfig
$ export UBOOT_CFG_CORTEXA=j784s4_evm_a72_defconfig
$ export TFA_BOARD=j784s4
$ export TFA_EXTRA_ARGS="K3_USART=0x8"
$ export OPTEE_PLATFORM=k3-j784s4
$ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
.. j784s4_evm_rst_include_start_build_steps
1. Trusted Firmware-A
.. include:: k3.rst
:start-after: .. k3_rst_include_start_build_steps_tfa
:end-before: .. k3_rst_include_end_build_steps_tfa
2. OP-TEE
.. include:: k3.rst
:start-after: .. k3_rst_include_start_build_steps_optee
:end-before: .. k3_rst_include_end_build_steps_optee
3. U-Boot
.. _j784s4_evm_rst_u_boot_r5:
* 3.1 R5
.. include:: k3.rst
:start-after: .. k3_rst_include_start_build_steps_spl_r5
:end-before: .. k3_rst_include_end_build_steps_spl_r5
.. _j784s4_evm_rst_u_boot_a72:
* 3.2 A72
.. include:: k3.rst
:start-after: .. k3_rst_include_start_build_steps_uboot
:end-before: .. k3_rst_include_end_build_steps_uboot
.. j784s4_evm_rst_include_end_build_steps
Target Images
-------------
In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
variant (GP, HS-FS, HS-SE) requires a different source for these files.
- GP
* tiboot3-j784s4-gp-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
* tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
- HS-FS
* tiboot3-j784s4-hs-fs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
* tispl.bin, u-boot.img from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
- HS-SE
* tiboot3-j784s4-hs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
* tispl.bin, u-boot.img from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
Image formats
-------------
- tiboot3.bin
.. image:: img/multi_cert_tiboot3.bin.svg
:alt: tiboot3.bin format
- tispl.bin
.. image:: img/dm_tispl.bin.svg
:alt: tispl.bin format
R5 Memory Map
-------------
.. list-table::
:widths: 16 16 16
:header-rows: 1
* - Region
- Start Address
- End Address
* - SPL
- 0x41c00000
- 0x41c40000
* - EMPTY
- 0x41c40000
- 0x41c61f20
* - STACK
- 0x41c65f20
- 0x41c61f20
* - Global data
- 0x41c65f20
- 0x41c66000
* - Heap
- 0x41c66000
- 0x41c76000
* - BSS
- 0x41c76000
- 0x41c80000
* - DM DATA
- 0x41c80000
- 0x41c84130
* - EMPTY
- 0x41c84130
- 0x41cff9fc
* - MCU Scratchpad
- 0x41cff9fc
- 0x41cffbfc
* - ROM DATA
- 0x41cffbfc
- 0x41cfffff
Switch Setting for Boot Mode
----------------------------
Boot Mode pins provide means to select the boot mode and options before the
device is powered up. After every POR, they are the main source to populate
the Boot Parameter Tables.
Boot Mode Pins for J784S4-EVM
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The following tables show some common boot modes used on J784S4 EVM platform.
More details can be found in the Technical Reference Manual:
http://www.ti.com/lit/zip/spruj52 under the `Boot Mode Pins` section.
.. list-table:: J784S4 EVM Boot Modes
:widths: 16 16 16
:header-rows: 1
* - Switch Label
- SW11: 12345678
- SW7: 12345678
* - SD
- 10000010
- 00000000
* - EMMC
- 10000000
- 01000000
* - OSPI
- 00000110
- 01000000
* - UART
- 00000000
- 01110000
For SW7 and SW11, the switch state in the "ON" position = 1.
Boot Mode Pins for AM69-SK
^^^^^^^^^^^^^^^^^^^^^^^^^^
The following table show some common boot modes used on AM69-SK platform.
More details can be found in the User Guide for AM69-SK:
https://www.ti.com/lit/ug/spruj70/spruj70.pdf under the `Bootmode Settings`
section.
.. list-table:: AM69 SK Boot Modes
:widths: 16 16
:header-rows: 1
* - Switch Label
- SW2: 1234
* - SD
- 0000
* - EMMC
- 0110
* - UART
- 1010
For SW2, the switch state in the "ON" position = 1.
Debugging U-Boot
----------------
See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
detailed setup information.
.. warning::
**OpenOCD support since**: September 2023 (git master)
Until the next stable release of OpenOCD is available in your development
environment's distribution, it might be necessary to build OpenOCD `from the
source <https://github.com/openocd-org/openocd>`_.
Debugging U-Boot on J784S4-EVM and AM69-SK
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.. include:: k3.rst
:start-after: .. k3_rst_include_start_openocd_connect_XDS110
:end-before: .. k3_rst_include_end_openocd_connect_XDS110
To start OpenOCD and connect to J784S4-EVM or AM69-SK board, use the
following.
.. code-block:: bash
openocd -f board/ti_j784s4evm.cfg
|