aboutsummaryrefslogtreecommitdiff
path: root/drivers/clk/ti/clk-am3-dpll-x2.c
blob: 3cf279d6a3a9763c8fd15573bda7026e84df3ba3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
// SPDX-License-Identifier: GPL-2.0+
/*
 * TI DPLL x2 clock support
 *
 * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
 *
 * Loosely based on Linux kernel drivers/clk/ti/dpll.c
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/clk-provider.h>

struct clk_ti_am3_dpll_x2_priv {
	struct clk parent;
};

static ulong clk_ti_am3_dpll_x2_get_rate(struct clk *clk)
{
	struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(clk->dev);
	unsigned long rate;

	rate = clk_get_rate(&priv->parent);
	if (IS_ERR_VALUE(rate))
		return rate;

	rate *= 2;
	dev_dbg(clk->dev, "rate=%ld\n", rate);
	return rate;
}

const struct clk_ops clk_ti_am3_dpll_x2_ops = {
	.get_rate = clk_ti_am3_dpll_x2_get_rate,
};

static int clk_ti_am3_dpll_x2_remove(struct udevice *dev)
{
	struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
	int err;

	err = clk_release_all(&priv->parent, 1);
	if (err) {
		dev_err(dev, "failed to release parent clock\n");
		return err;
	}

	return 0;
}

static int clk_ti_am3_dpll_x2_probe(struct udevice *dev)
{
	struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
	int err;

	err = clk_get_by_index(dev, 0, &priv->parent);
	if (err) {
		dev_err(dev, "%s: failed to get parent clock\n", __func__);
		return err;
	}

	return 0;
}

static const struct udevice_id clk_ti_am3_dpll_x2_of_match[] = {
	{.compatible = "ti,am3-dpll-x2-clock"},
	{}
};

U_BOOT_DRIVER(clk_ti_am3_dpll_x2) = {
	.name = "ti_am3_dpll_x2_clock",
	.id = UCLASS_CLK,
	.of_match = clk_ti_am3_dpll_x2_of_match,
	.probe = clk_ti_am3_dpll_x2_probe,
	.remove = clk_ti_am3_dpll_x2_remove,
	.priv_auto = sizeof(struct clk_ti_am3_dpll_x2_priv),
	.ops = &clk_ti_am3_dpll_x2_ops,
};