1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
*/
#include <common.h>
#include <asm/arch/regs.h>
#include <asm/io.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
#include <init.h>
#include <linux/bitops.h>
#include <linux/sizes.h>
#include <linux/delay.h>
#include <ram.h>
#include <reset.h>
#include "starfive_ddr.h"
DECLARE_GLOBAL_DATA_PTR;
struct starfive_ddr_priv {
struct udevice *dev;
struct ram_info info;
void __iomem *ctrlreg;
void __iomem *phyreg;
struct reset_ctl_bulk rst;
struct clk clk;
u32 fre;
};
static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *priv)
{
enum ddr_size_t size;
switch (priv->info.size) {
case SZ_2G:
size = DDR_SIZE_2G;
break;
case SZ_4G:
size = DDR_SIZE_4G;
break;
case 0x200000000:
size = DDR_SIZE_8G;
break;
case 0x400000000:
default:
pr_err("unsupport size %lx\n", priv->info.size);
return -EINVAL;
}
ddr_phy_train(priv->phyreg + (PHY_BASE_ADDR << 2));
ddr_phy_util(priv->phyreg + (PHY_AC_BASE_ADDR << 2));
ddr_phy_start(priv->phyreg, size);
DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
ddrcsr_boot(priv->ctrlreg, priv->ctrlreg + SEC_CTRL_ADDR,
priv->phyreg, size);
return 0;
}
static int starfive_ddr_probe(struct udevice *dev)
{
struct starfive_ddr_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
u64 rate;
int ret;
/* Read memory base and size from DT */
fdtdec_setup_mem_size_base();
priv->info.base = gd->ram_base;
priv->info.size = gd->ram_size;
priv->dev = dev;
addr = dev_read_addr_index(dev, 0);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->ctrlreg = (void __iomem *)addr;
addr = dev_read_addr_index(dev, 1);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->phyreg = (void __iomem *)addr;
ret = dev_read_u32(dev, "clock-frequency", &priv->fre);
if (ret)
return ret;
switch (priv->fre) {
case 2133:
rate = 1066000000;
break;
case 2800:
rate = 1400000000;
break;
default:
pr_err("Unknown DDR frequency %d\n", priv->fre);
return -EINVAL;
};
ret = reset_get_bulk(dev, &priv->rst);
if (ret)
return ret;
ret = reset_deassert_bulk(&priv->rst);
if (ret < 0)
return ret;
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret)
goto err_free_reset;
ret = clk_set_rate(&priv->clk, rate);
if (ret < 0)
goto err_free_reset;
ret = starfive_ddr_setup(dev, priv);
printf("DDR version: dc2e84f0.\n");
return ret;
err_free_reset:
reset_release_bulk(&priv->rst);
return ret;
}
static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info)
{
struct starfive_ddr_priv *priv = dev_get_priv(dev);
*info = priv->info;
return 0;
}
static struct ram_ops starfive_ddr_ops = {
.get_info = starfive_ddr_get_info,
};
static const struct udevice_id starfive_ddr_ids[] = {
{ .compatible = "starfive,jh7110-dmc" },
{ }
};
U_BOOT_DRIVER(starfive_ddr) = {
.name = "starfive_ddr",
.id = UCLASS_RAM,
.of_match = starfive_ddr_ids,
.ops = &starfive_ddr_ops,
.probe = starfive_ddr_probe,
.priv_auto = sizeof(struct starfive_ddr_priv),
};
|
