aboutsummaryrefslogtreecommitdiff
path: root/dts/upstream/Bindings/media/nxp,imx8-isi.yaml
blob: 4d5348d456a1fedf8b98b405dc1c278dfdeed797 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX8 Image Sensing Interface

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description: |
  The Image Sensing Interface (ISI) combines image processing pipelines with
  DMA engines to process and capture frames originating from a variety of
  sources. The inputs to the ISI go through Pixel Link interfaces, and their
  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.

properties:
  compatible:
    enum:
      - fsl,imx8mn-isi
      - fsl,imx8mp-isi
      - fsl,imx93-isi

  reg:
    maxItems: 1

  clocks:
    items:
      - description: The AXI clock
      - description: The APB clock
      # TODO: Check if the per-channel ipg_proc_clk clocks need to be specified
      # as well, in case some SoCs have the ability to control them separately.
      # This may be the case of the i.MX8[DQ]X(P)

  clock-names:
    items:
      - const: axi
      - const: apb

  fsl,blk-ctrl:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      A phandle referencing the block control that contains the CSIS to ISI
      gasket.

  interrupts:
    description: Processing pipeline interrupts, one per pipeline
    minItems: 1
    maxItems: 2

  power-domains:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description: |
      Ports represent the Pixel Link inputs to the ISI. Their number and
      assignment are model-dependent. Each port shall have a single endpoint.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - fsl,blk-ctrl
  - ports

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,imx8mn-isi
              - fsl,imx93-isi
    then:
      properties:
        interrupts:
          maxItems: 1
        ports:
          properties:
            port@0:
              description: MIPI CSI-2 RX
            port@1: false
          required:
            - port@0

  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8mp-isi
    then:
      properties:
        interrupts:
          maxItems: 2
        ports:
          properties:
            port@0:
              description: MIPI CSI-2 RX 0
            port@1:
              description: MIPI CSI-2 RX 1
          required:
            - port@0
            - port@1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mn-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/imx8mn-power.h>

    isi@32e20000 {
        compatible = "fsl,imx8mn-isi";
        reg = <0x32e20000 0x100>;
        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
                 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
        clock-names = "axi", "apb";
        fsl,blk-ctrl = <&disp_blk_ctrl>;
        power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                isi_in: endpoint {
                    remote-endpoint = <&mipi_csi_out>;
                };
            };
        };
    };

  - |
    #include <dt-bindings/clock/imx8mp-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    isi@32e00000 {
        compatible = "fsl,imx8mp-isi";
        reg = <0x32e00000 0x4000>;
        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
                 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
        clock-names = "axi", "apb";
        fsl,blk-ctrl = <&media_blk_ctrl>;
        power-domains = <&mediamix_pd>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                isi_in_0: endpoint {
                    remote-endpoint = <&mipi_csi_0_out>;
                };
            };

            port@1 {
                reg = <1>;
                isi_in_1: endpoint {
                    remote-endpoint = <&mipi_csi_1_out>;
                };
            };
        };
    };
...